Spectrum Brands MC.31XX Fifo Mode, General Information, Background Fifo Read, Speed Limitations

FIFO Mode Overview

FIFO Mode

Overview

General Information

The FIFO mode allows to record data continuously and trans- fer it online to the PC (acquisition boards) or allows to write data continuously from the PC to the board (generation boards). Therefore the on-board memory of the board is used as a continuous buffer. On the PC the data can be used for any calculation or can be written to hard disk while recording is running (acquisition boards) or the data can be read from hard disk and calculated online before writing it to the board.

FIFO mode uses interrupts and is supported by the drivers on 32 bit operating systems like Window 9x/ME, Windows NT/2000/XP or Linux. Start of FIFO mode waits for a trigger event. If you wish to start FIFO mode immediately, you may use the software trigger.FIFO mode can be used together with the options Multiple Recording/Replay and Gated Sampling/Replay. Details on this can be found in the appropriate chapters about the options.

Background FIFO Read

On the hardware side the board memory is spilt in two buffers of the same length. These buffers can be up to half of the on-board memory in size. In addition to the hardware buffers the driver holds up to 256 software buffers of the same length as the hardware buffers are. When- ever a hardware buffer is full with data the hardware generates an interrupt and the driver transfers this hardware buffer to the next software buffer that is available. While transfering one buffer to the PC, the other one is filled up with data. The driver is doing this job automatically in the background.

After the driver has finsihed transferring the data, the application software gets a signal and can process data (e.g stores data to hard disk or makes some calculations). After processing the data the application software tells the driver that he can again use the software buffer for acquisition data.

This two stages buffering has big advantages when running FIFO mode at the speed limit. The software buffers extremly expand the acquisi- tion time that can be buffered and protects the whole system against buffer overruns.

Speed Limitations

The FIFO mode is running continuously all the time. Therefore the data must be read out from the board (data acquisition) or written to the board (data generation) at least with the same speed that it is recorded/replayed. If data is read out from the board or written to the board slower, the hardware buffers will overrun at a certain point and FIFO mode is stopped.

One bottleneck with the FIFO mode is the PCI bus. The standard PCI bus is theoretically capable of transferring data with 33 MHz and 32 Bit. As a result a maximum burst transfer rate of 132 MByte per second can be achieved. As several devices can share the PCI bus this maximum transfer rate is only available to a short transfer burst until a new bus arbitration is necessray. In real life the continuous transfer rate is limited to approximately 100-110 MBytes per second. The maximum FIFO speed one can achieve heavily depends on the PC system and the operating system and varies from system to system.

The maximum sample rate one can run in continuous FIFO mode depends on the number of activated channels:

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