Option Gated SamplingTrigger modes
Resulting start delays
Sample rate | Activated channels |
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| external TTL trigger | internal trigger | ext. TTL trigger with | internal trigger with | ||||
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
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| activated | activated |
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| synchronization | synchronization | ||||||||
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< 5 MS/s | x |
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| +4 samples | +5 samples | ||
> 5 MS/s | x |
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| +4 samples | +16 samples | +5 samples | +17 samples |
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< 5 MS/s | x |
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| +4 samples | +5 samples | ||
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> 5 MS/s | x |
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| +4 samples | +16 samples | +5 samples | +17 samples |
< 2.5 MS/s | x | x |
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| +4 samples | +5 samples | ||
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> 2.5 MS/s | x | x |
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| +2 samples | +10 samples | +3 samples | +11 samples |
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< 2.5 MS/s | x | x |
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| +4 samples | +5 samples | ||
> 2.5 MS/s | x | x |
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| +2 samples | +10 samples | +3 samples | +11 samples |
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< 1.25 MS/s | x | x | x | x |
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| +5 samples | +5 samples | ||
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> 1.25 MS/s | x | x | x | x |
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| +8 samples | +9 samples | ||
< 1.25 MS/s | x | x | x | x | x | x | x | x | +5 samples | +5 samples | ||
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> 1.25 MS/s | x | x | x | x | x | x | x | x | +8 samples | +9 samples | ||
Number of samples on gate signal
As described above there’s a delay at the start of the gate interval due to the internal memory structure. However this delay can be partly compensated by internal pipelines resulting in a data delay that even can be negative showing the trigger event (acquisition mode only). This data delay is listed in an extra table. But beneath this compensation there’s still the start delay that as a result causes the card to use less samples than the gate signal length. Please refer to the following table to see how many samples less than the length of gate signal are used
Module 0 |
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0 | 1 | 2 | 3 | 0 | 1 | 2 | 3 | Mode | Sampling clock | less samples | Sampling clock | less samples |
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| Standard/FIFO | < 5 MS/s | 7 | > 5 MS/s | 12 |
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| Standard | < 5 MS/s | 7 | > 5 MS/s | 12 |
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| FIFO | < 2.5 MS/s | 3 | > 2.5 MS/s | 6 |
X | X |
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| Standard/FIFO | < 2.5 MS/s | 3 | > 2.5 MS/s | 6 |
X | X |
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| Standard | < 2.5 MS/s | 3 | > 2.5 MS/s | 6 |
X | X |
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| X | X |
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| FIFO | < 1.25 MS/s | 2 | > 1.25 MS/s | 3 |
X | X | X | X |
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| Standard/FIFO | < 1.25 MS/s | 2 | > 1.25 MS/s | 3 |
X | X | X | X | X | X | X | X | Standard | < 1.25 MS/s | 2 | > 1,25 MS/s | 3 |
X | X | X | X | X | X | X | X | FIFO | < 625 kS/s | 1 | > 625 kS/s | 2 |
Allowed trigger modes
As mentioned above not all of the possible trigger modes can be used as a gate condition. The following table is showing the allowed trigger modes that can be used and explains the event that has to be detected for
External TTL edge trigger
The following table shows the allowed trigger modes when using the external TTL trigger connector:
Mode | Gate start will be detected on | Gate end will be detected on |
TM_TTLPOS | positive edge on external trigger | negative edge on external trigger |
TM_TTL_NEG | negative edge on external trigger | positive edge on external trigger |
External TTL pulsewidth trigger
The following table shows the allowed pulsewidth trigger modes when using the external TTL trigger connector:
Mode | Gate start will be detected on | Gate end will be detected on |
TM_TTLHIGH_LP | high pulse of external trigger longer than programmed pulsewidth | negative edge on external trigger |
TM_TTLLOW_LP | low pulse of external trigger longer than programmed pulsewidth | positive edge on external trigger |
(c) Spectrum GmbH | 81 |
