Hardware information | Introduction |
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Hardware information
Block diagram
Technical Data
Resolution |
| 12 bit |
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| Dimension |
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| 160 x 233 mm (Standard 6U) |
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Differential linearity error |
| ≤ 1 LSB (ADC) |
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| Width (Standard) |
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| 1 slot |
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Integral linearity error |
| ≤ 2.5 LSB (ADC) |
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| Width (with digital inputs) |
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| 2 slots |
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Multi: Trigger to 1st sample delay | fix |
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| Connector |
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| 3 mm SMB male |
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Multi: Recovery time |
| < 20 samples |
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| Input impedance |
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| 50 Ohm / 1 MOhm 25 pF |
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ext. Trigger accuracy |
| 1 Samples |
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| Overvoltage protection (range ≤ ±1 V) |
| ±5 V |
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int. Trigger accuracy |
| 1 Sample |
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| Overvoltage protection (range > ±1 V) |
| ±50 V |
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Ext. clock: delay to internal clock | 42 ns ±2 ns |
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| Warm up time |
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| 10 minutes |
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input signal with 50 ohm termination | max 5 V rms |
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| Operating temperature |
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| 0°C - 50°C |
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Digital Inputs input impedance |
| 110 Ohm @ 2.5 V |
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| Storage temperature |
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Digital Inputs delay to analog sample |
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| Humidity |
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| 10% to 90% |
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Min internal clock |
| 1 kS/s |
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Min external clock |
| 1 kS/s |
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| Power consumption 5 V @ |
| full speed |
| max. 3.3 A (16.5 Watt) |
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| Power consumption 5 V @ power down |
| max. 2.5 A (12.5 Watt) |
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Trigger input:Standard TTL level |
| Low: |
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| Clock input: Standard TTL level |
| Low: |
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| High: 2.0 V > level < 5.5 V |
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| High: 2.0 V > level < 5.5 V |
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| Trigger pulse must be valid > 2 clock periods. |
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| Rising edge. Duty cycle: 50% ± 5% | ||||||||||||||
Trigger output |
| Standard TTL, capable of driving 50 Ohm. |
| Clock output |
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| Standard TTL, capable of driving 50 Ohm | ||||||||||||||||
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| Low < 0.4 V (@ 20 mA, max 64 mA) |
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| Low < 0.4 V (@ 20 mA, max 64 mA) | |||||||||||
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| High > 2.4 V (@ |
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| High > 2.4 V (@ | |||||||||||
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| One positive edge after the first internal trigger |
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Input range |
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| ±50 mV |
| ±100 mV |
| ±200 mV |
| ±500 mV |
| ±1 V |
| ±2 V |
| ±5 V |
| ±10 V | ||||||
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Software programmable offset |
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| ±50 mV |
| ±100 mV |
| ±200 mV |
| ±500 mV |
| ±1 V |
| ±2 V |
| ±5 V |
| ±10 V | ||||||
Offset error |
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| < 1 LSB, adjustable by user |
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Gain error |
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| < 1 % |
| < 1 % |
| < 1 % |
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| < 1 % |
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| < 1 % |
| < 1 % |
| < 1 % |
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Noise (rms): 50 Ohm, 25 MS/s |
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| < 1.5 LSB |
| < 1.2 LSB |
| < 1.0 LSB |
| < 1.0 LSB |
| < 1.0 LSB |
| < 1.0 LSB |
| < 1.0 LSB |
| < 1.0 LSB | ||||||
Crosstalk 500 kHz signal, ±50 mV input, 50 Ohm |
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| MC.3110 |
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| MC.3112 |
| MC.3120 |
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| MC.3122 |
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| MC.3130 |
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| MC.3132 |
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| MC.3111 |
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| MC.3121 |
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| MC.3131 |
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max internal clock |
| 1 MS/s |
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| 1 MS/s |
| 10 MS/s |
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| 10 MS/s |
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| 25 MS/s |
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| 25 MS/s |
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max external clock |
| 1 MS/s |
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| 1 MS/s |
| 10 MS/s |
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| 10 MS/s |
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| 25 MS/s |
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| 25 MS/s |
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| > 500 kHz |
| > 500 kHz |
| > 5 MHz |
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| > 5 MHz |
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| > 12.5 MHz |
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| > 12.5 MHz |
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12 | MC.31xx Manual |
