Sample format

FIFO Mode	Programming

The following example shows how to sort the channel data when using 4 channels in FIFO mode:

for (i = 0; i < (lBufferSizeInSamples / 4); i++)

{

Data[0][i] = FIFOBuffer[i * 4 + 0];

Data[1][i] = FIFOBuffer[i * 4 + 2];

Data[2][i] = FIFOBuffer[i * 4 + 1];

Data[3][i] = FIFOBuffer[i * 4 + 3];

}

The sample format in FIFO mode does not differ from the one of the standard (non FIFO) mode. Please refer to the relating passage concerning the sample format in the standard acquisition chapter.

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Image 57

Spectrum Brands MC.31XX manual Sample format

Contents

English version April 27 MC.31xxPage Software Driver Installation Hardware InstallationIntroduction Software Programming the Board Fifo ModeAnalog Inputs Standard acquisition modes Option Gated Sampling Option Multiple RecordingOption Timestamp Option Extra I/O Preface IntroductionGeneral Information Preface Different models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Digital inputs Additional optionsExtra I/O Option -XMF Introduction Additional options Timestamp Starhub Spectrum type plate Hardware information Block diagram Technical Data Order information Dynamic ParametersIntroductionHardware information Order No Description Hardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Mounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cables Installing multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Software Driver Installation Windows InstallationWindows Version control Driver Update Windows Driver Update Windows XP Software Driver Installation Windows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Overview Linux Now it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driver Software Overview SoftwareFirst Test with SBench Software Overview Header files ++ Driver InterfaceMicrosoft Visual C++ Borland C++ Builder National Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include Drivers Function SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData Windows Type definition Delphi Pascal Programming InterfaceInclude Driver Examples Software Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tables Initialization Example for error checkingStarting the automatic initialization routine PCI Register Installed features and options Installed memoryHardware version Date of production Used type of driver Used interrupt lineProgramming the Board Initialization Driver version Example program for the board initialization Powerdown and resetSpcpcimemsize Spcpciserialno Channel Selection Analog InputsImportant note on channels selection Analog Inputs Rerouting information for module Channel reroutingSPCCHROUTE0 SPCCHROUTE1 Input ranges Setting up the inputs Register Value Direction Description Offset range Input offset Automatical adjustment of the offset settings Overrange bitInput termination Spcadjsave ADJUSER0 Spcadjautoadj Adjall Programming Standard acquisition modesMemory, Pre- and Posttrigger Pretrigger = memsize posttrigger Command register Starting without interrupt classic modeMaximum posttrigger in MSamples Minimum memsize and posttrigger in samples Starting with interrupt driven mode Standard acquisition modes ProgrammingStatus register Fast 8 bit mode Normal mode201100 Enables the fast 8 bit mode Data organization Reading out the data with SpcGetData Standard modeValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer value Programming General Information Fifo ModeBackground Fifo Read Speed Limitations Software Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffers Buffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boards Fifo acquisition example Example Fifo acquisition modeSpcfifostart Spcfifowait Sample format Clock generation Internally generated sample rateStandard internal sample rate Maximum internal sample rate in MS/s normal mode Using plain quartz without PLLExternal reference clock Clock generation Direct external clock External clockingMinimum external sample rate Maximum external samplerate in MS/s External clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo General Description Trigger modes and appendant registersSoftware trigger External TTL trigger Edge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL trigger Positive and negative TTL trigger Pulsewidth triggersTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulses TTL pulsewidth trigger for short LOW pulses TTL pulsewidth trigger for long LOW pulsesSpctriggermode Tmttlhighlp Spcpulsewidth Overview of the channel trigger registers Channel TriggerSpctriggermode Tmchannel Tmchxoff Spctriggermode Tmchor TriggerlevelSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 Tmchxoff SPCTRIGGERMODE0 Tmchxpos Reading out the number of possible trigger levelsSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mV Channel trigger on positive edge Detailed description of the channel trigger modesChannel trigger on negative edge Channel trigger on positive and negative edge Channel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulses Channel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulses Channel window trigger for leaving signals Channel window trigger for entering signals Channel window trigger for long outer signals Channel window trigger for long inner signals Channel window trigger for short outer signals Channel window trigger for short inner signals When using Multiple Recording pretrigger is not available Standard ModeOption Multiple Recording Recording modes Trigger modesOption Multiple Recording Resulting start delaysSpcmemsize Spctriggermode Option Gated Sampling General information and trigger delayOption Gated Sampling Spcgate Alignement samples per channel End of gate alignement Allowed trigger modes Number of samples on gate signalOption Gated SamplingTrigger modes External TTL edge trigger Example program Option Gated Sampling Example programChannel trigger Spctriggermode Tmttlpos Option Timestamp StartReset modeTimestamp modes Limits Functions for accessing the data RefClock mode optionalTimestamp Status Reading out timestamp data Data format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Digital I/Os Option Extra I/OAnalog Outputs Channel direction Programming example Option Extra I/O Programming example Option Digital inputs Bit Standard Mode Digital Inputs enabledSample format Spcreaddigital Different synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhub Set up the board parameters Setup order for the different synchronization optionsLet the master calculate it’s clocking Write Data to on-board memory output boards only Define the boards for trigger master Example for data writingExample of board #2 set as trigger master 4a Define synchronization or trigger Example board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronization Wait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Restarting the board for another synchronized run 2a Write first data for output boards Example of Fifo buffer allocationSpcsyncmasterfifo Spcsyncslavefifo General information Additions for synchronizing different boards 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividers Board type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131 Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample rates Error Codes Error CodesError name Value hex Value dec Error description Appendix Pin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable