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Spectrum Brands MC.31XX SumSampleRateNSampleRate=NActChPerModuleN, , SyncSpeed

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Synchronization (Option) Setup synchronization for use with FIFO mode and equally clokked boards

(c) Spectrum GmbH 97

All clock rates of all synchronized boards are derived from the clock signal that is distributed via the sync bus. This clock is the sum samplerate

of one module of the clock master board. Based on this speed the clock rates of the slave boards can be set. As these clock rates are divided

from the sync clock, the board with the maximum sum sample rate should be set up as clock master.

Calculating the clock dividers

The sum sample rate can easily be calculated by the formula on the right.

The value for the sample rate of board N must contain the actual desired

conversion rate for one channel of board N. Please refer to the dedicated

chapter in the board’s manual to get informed about the relation beween

the board model and the number of actually activated channels per mod-

ule for the different channel setups.

As mentioned above the board with the highest sum sample rate must be

set up as the clock master. This maximum sum sample rate is used as the

overall sync speed, which is distributed via the sync bus. If you have cal-

culated the sync speed you can calculate the clock dividers for the differ-

ent boards with the formula on the right.

The maximum possible channels per module for all Spectrum boards are

given in the table below.

20xx x30xx x31xx x40xx x45xx x60xx x61xx x70xx x72xx x

0x 7005 1

1x 3010 1 3110 2 6110 2 7010 1 7210 1

3011 2 3111 4 6011 2 6111 2 7011 2 7211 1

3012 2 3112 4 6012 2

3013 2

3014 2

3015 1

3016 2

2x 2020 2 3020 1 3120 2 4020 1 4520 2 7020 1 7220 1

2021 2 3021 2 3121 4 4021 2 4521 2 6021 2 7021 2 7221 1

3022 2 3122 4 4022 2 6022 2

3023 2

3024 2

3025 1

3026 2

3027 1

3x 3130 2 4030 1 4530 2 6030 1

2031 2 3031 2 3131 4 4031 2 4531 2 6031 1

3132 4 4032 2

2033 2 3033 2 6033 2

6034 2

4x 4540 2

4541 2

SumSampleRateNSampleRate=NActChPerModuleN⋅

SyncSpeed

Contents

Main Page Page Page Page Introduction Preface General Information Different models of the MC.31xx series Page Additional options Digital inputs Extra I/O (Option -XMF) Starhub Timestamp The Spectrum type plate 12 MC.31xx Manual Hardware information Introduction Hardware information Block diagram Technical Data Introduction Hardware information (c) Spectrum GmbH 13 Dynamic Parameters Order information Hardware Installation System Requirements Warnings ESD Precautions Cooling Precautions Installing a board with digital inputs/outputs Installing a board with extra I/O (Option -XMF) Installing multiple boards synchronized by starhub Installing multiple synchronized boards Software Driver Installation Interrupt Sharing Windows 98 Page Windows 2000 Page Windows XP Page Windows NT Adding boards to the Windows NT driver Linux Overview Page Software Software Overview First Test with SBench C/C++ Driver Interface Header files Microsoft Visual C++ Borland C++ Builder Linux Gnu C Other Windows C/C++ compilers National Instruments LabWindows/CVI Page Delphi (Pascal) Programming Interface Type definition Include Driver Examples Page Visual Basic Programming Interface Include Driver Visual Basic Examples VBA for Excel Examples Page Programming the Board Register tables Programming examples Error handling Initialization Starting the automatic initialization routine PCI Register Hardware version Date of production Serial number Maximum possible sample rate Installed memory Used interrupt line Used type of driver Powerdown and reset Analog Inputs Channel Selection Important note on channels selection Channel rerouting Setting up the inputs Input ranges Input offset Overrange bit Input termination Automatical adjustment of the offset settings Page Standard acquisition modes General Information Programming Memory, Pre- and Posttrigger Starting without interrupt (classic mode) Starting with interrupt driven mode Data organization Sample format Reading out the data with SpcGetData Page FIFO Mode General Information Background FIFO Read Speed Limitations Programming Software Buffers Buffer processing FIFO mode Example FIFO acquisition mode Data organization Sample format Clock generation Internally generated sample rate Standard internal sample rate Using plain quartz without PLL External reference clock External clocking Direct external clock External clock with divider Trigger modes and appendant registers General Description Software trigger External TTL trigger Edge triggers Pulsewidth triggers Page Channel Trigger Overview of the channel trigger registers Triggerlevel Page Detailed description of the channel trigger modes Page Page Page Page Page Page Page Option Multiple Recording Recording modes Standard Mode FIFO Mode Trigger modes Resulting start delays Option Gated Sampling Recording modes Standard Mode FIFO Mode Trigger modes End of gate alignement Alignement samples per channel Resulting start delays Number of samples on gate signal Allowed trigger modes Example program Option Timestamp General information = Limits Timestamp modes Timestamp Status Reading out timestamp data Functions for accessing the data Data format Example programs Option Timestamp Example programs Standard acquisition mode Acquisition with Multiple Recording Option Extra I/O Digital I/Os Channel direction Transfer Data Analog Outputs Programming example Option Digital inputs Synchronization (Option) The different synchronization options Synchronization with option cascading Synchronization with option starhub The setup order for the different synchronization options Setup Order for use with standard (non FIFO) mode and equally clocked boards Page Page Setup synchronization for use with FIFO mode and equally clokked boards Page Additions for synchronizing different boards SumSampleRateNSampleRate=NActChPerModuleN SyncSpeed Page Additions for equal boards with different sample rates Resulting delays using different boards or speeds = ResultingDelay ClockMasterDelay ClockSlaveDelayN 100 MC.31xx Manual Appendix Error Codes Pin assignment of the multipin connector Extra I/O with external connector(Option -XMF) Option Digital inputs Pin assignment of the multipin cable