Calculating the clock dividers | Spectrum Brands MC.31XX specification

Synchronization (Option)	Setup synchronization for use with FIFO mode and equally clokked boards

All clock rates of all synchronized boards are derived from the clock signal that is distributed via the sync bus. This clock is the sum samplerate of one module of the clock master board. Based on this speed the clock rates of the slave boards can be set. As these clock rates are divided from the sync clock, the board with the maximum sum sample rate should be set up as clock master.

Calculating the clock dividers

The sum sample rate can easily be calculated by the formula on the right. The value for the sample rate of board N must contain the actual desired conversion rate for one channel of board N. Please refer to the dedicated chapter in the board’s manual to get informed about the relation beween the board model and the number of actually activated channels per mod- ule for the different channel setups.

As mentioned above the board with the highest sum sample rate must be set up as the clock master. This maximum sum sample rate is used as the overall sync speed, which is distributed via the sync bus. If you have cal- culated the sync speed you can calculate the clock dividers for the differ- ent boards with the formula on the right.

The maximum possible channels per module for all Spectrum boards are given in the table below.

SumSampleRateN = SampleRateN ⋅ ActChPerModuleN

SyncSpeed

	20xx	x	30xx	x	31xx	x	40xx	x	45xx	x	60xx	x	61xx	x	70xx	x	72xx	x
0x															7005	1


1x			3010	1	3110	2							6110	2	7010	1	7210	1

			3011	2	3111	4					6011	2	6111	2	7011	2	7211	1

			3012	2	3112	4					6012	2
			3013	2

			3014	2

			3015	1
			3016	2


2x	2020	2	3020	1	3120	2	4020	1	4520	2					7020	1	7220	1
	2021	2	3021	2	3121	4	4021	2	4521	2	6021	2			7021	2	7221	1
			3022	2	3122	4	4022	2			6022	2

			3023	2
			3024	2
			3025	1

			3026	2
			3027	1

3x					3130	2	4030	1	4530	2	6030	1
	2031	2	3031	2	3131	4	4031	2	4531	2	6031	1
					3132	4	4032	2

	2033	2	3033	2							6033	2
											6034	2

4x									4540	2
									4541	2

(c) Spectrum GmbH

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Spectrum Brands MC.31XX manual Calculating the clock dividers, 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx

Contents

English version April 27 MC.31xxPage Software Driver Installation Hardware InstallationIntroduction Software Programming the Board Fifo ModeAnalog Inputs Standard acquisition modes Option Gated Sampling Option Multiple RecordingOption Timestamp Option Extra I/O Preface IntroductionGeneral Information Preface MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131 Different models of the MC.31xx seriesIntroduction MC.3112 MC.3122 MC.3132 Digital inputs Additional optionsExtra I/O Option -XMF Introduction Additional options Timestamp Starhub Spectrum type plate Hardware information Block diagram Technical Data Order information Dynamic ParametersIntroductionHardware information Order No Description Installing the board in the system Hardware InstallationSystem Requirements Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputsHardware Installation Mounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cables Installing multiple synchronized boards Interrupt Sharing Software Driver InstallationInterrupt Sharing Software Driver Installation Windows InstallationWindows Version control Driver Update Windows Driver Update Windows XP Software Driver Installation Windows XP Windows NT Software Driver Installation Windows NTAdding boards to the Windows NT driver Overview Linux Now it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driver Software Overview SoftwareFirst Test with SBench Software Overview Header files ++ Driver InterfaceMicrosoft Visual C++ Borland C++ Builder National Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include Drivers Function SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData Windows Type definition Delphi Pascal Programming InterfaceInclude Driver Examples Software Visual Basic Examples Visual Basic Programming InterfaceVBA for Excel Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tables Initialization Example for error checkingStarting the automatic initialization routine PCI Register Installed features and options Installed memoryHardware version Date of production Used type of driver Used interrupt lineProgramming the Board Initialization Driver version Example program for the board initialization Powerdown and resetSpcpcimemsize Spcpciserialno Channel Selection Analog InputsImportant note on channels selection Analog Inputs Rerouting information for module Channel reroutingSPCCHROUTE0 SPCCHROUTE1 Input ranges Setting up the inputs Register Value Direction Description Offset range Input offset Overrange bit Automatical adjustment of the offset settingsInput termination Spcadjsave ADJUSER0 Spcadjautoadj Adjall Programming Standard acquisition modesMemory, Pre- and Posttrigger Pretrigger = memsize posttrigger Command register Starting without interrupt classic modeMaximum posttrigger in MSamples Minimum memsize and posttrigger in samples Standard acquisition modes Programming Starting with interrupt driven modeStatus register Fast 8 bit mode Normal mode201100 Enables the fast 8 bit mode Data organization Reading out the data with SpcGetData Standard modeValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer value Programming General Information Fifo ModeBackground Fifo Read Speed Limitations Software Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffers Buffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boards Fifo acquisition example Example Fifo acquisition modeSpcfifostart Spcfifowait Sample format Internally generated sample rate Clock generationStandard internal sample rate Maximum internal sample rate in MS/s normal mode Using plain quartz without PLLExternal reference clock Clock generation Direct external clock External clockingMinimum external sample rate Maximum external samplerate in MS/s CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerFifo General Description Trigger modes and appendant registersSoftware trigger External TTL trigger Edge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL trigger Positive and negative TTL trigger Pulsewidth triggersTTL pulsewidth trigger for long High pulses TTL pulsewidth trigger for short High pulses TTL pulsewidth trigger for short LOW pulses TTL pulsewidth trigger for long LOW pulsesSpctriggermode Tmttlhighlp Spcpulsewidth Overview of the channel trigger registers Channel TriggerSpctriggermode Tmchannel Tmchxoff Spctriggermode Tmchor TriggerlevelSPCTRIGGERMODE0 Tmchxoff SPCTRIGGERMODE2 Tmchxoff SPCTRIGGERMODE0 Tmchxpos Reading out the number of possible trigger levelsSPCHIGHLEVEL0 Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mV Channel trigger on positive edge Detailed description of the channel trigger modesChannel trigger on negative edge Channel trigger on positive and negative edge Channel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for short negative pulses Channel pulsewidth trigger for short positive pulsesTmchxposgsp Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulses Channel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulses Channel window trigger for leaving signals Channel window trigger for entering signals Channel window trigger for long outer signals Channel window trigger for long inner signals Channel window trigger for short outer signals Channel window trigger for short inner signals When using Multiple Recording pretrigger is not available Standard ModeOption Multiple Recording Recording modes Trigger modesOption Multiple Recording Resulting start delaysSpcmemsize Spctriggermode Option Gated Sampling General information and trigger delayOption Gated Sampling Spcgate Alignement samples per channel End of gate alignement Allowed trigger modes Number of samples on gate signalOption Gated SamplingTrigger modes External TTL edge trigger Example program Option Gated Sampling Example programChannel trigger Spctriggermode Tmttlpos Option Timestamp StartReset modeTimestamp modes Limits Functions for accessing the data RefClock mode optionalTimestamp Status Reading out timestamp data SpcGetData nr, ch, start, len, data Data formatSpctimestampcount Example programs Standard acquisition modeAcquisition with Multiple Recording Digital I/Os Option Extra I/OAnalog Outputs Channel direction Programming example Option Extra I/O Programming example Option Digital inputs Bit Standard Mode Digital Inputs enabledSample format Spcreaddigital Different synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhub Set up the board parameters Setup order for the different synchronization optionsLet the master calculate it’s clocking Write Data to on-board memory output boards only Define the boards for trigger master Example for data writingExample of board #2 set as trigger master 4a Define synchronization or trigger Example board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronization Wait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Restarting the board for another synchronized run 2a Write first data for output boards Example of Fifo buffer allocationSpcsyncmasterfifo Spcsyncslavefifo General information Additions for synchronizing different boards 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividers Board type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131 Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample rates Error Codes Error CodesError name Value hex Value dec Error description Appendix Extra I/O with external connectorOption -XMF Pin assignment of the multipin connectorOption Digital inputs Pin assignment of the multipin cable