Spectrum Brands MC.31XX manual

Trigger modes and appendant registers	Channel Trigger

Channel window trigger for long inner signals

The analog input is continuously sampled with the selected sample rate. The upper and the lower levels define a win- dow. Every time the signal enters the window from the out- side, the pulsewidth counter is startet. If the signal leaves the window before the pulsewidth counter has stopped, no trigger will be detected.

If the pulsewidth counter stops and the signal is still inside the window, the triggerevent will be detected.

Register	Value	Direction	set to	Value
SPC_TRIGGERMODE	40000	r/w	TM_CHANNEL	20040
SPC_TRIGGERMODE0	40200	r/w	TM_CHXWINENTER_LP	10041

SPC_HIGHLEVEL0	42000	r/w	Sets the window’s upper level relatively to the channel’s input range.	board dependant

SPC_LOWLEVEL0	42100	r/w	Sets the window’s lower level relatively to the channel’s input range.	board dependant
SPC_PULSEWIDTH	44000	r/w	Set to the desired pulsewidth in samples.	2 to 255

Channel window trigger for long outer signals

The analog input is continuously sampled with the selected sample rate. The upper and the lower levels define a win- dow. Every time the signal leaves the window from the in- side, the pulsewidth counter is startet. If the signal enters the window before the pulsewidth counter has stopped, no trig- ger will be detected.

If the pulsewidth counter stops and the signal is still outside the window, the triggerevent will be detected.

Register	Value	Direction	set to	Value
SPC_TRIGGERMODE	40000	r/w	TM_CHANNEL	20040
SPC_TRIGGERMODE0	40200	r/w	TM_CHXWINLEAVE_LP	10051

SPC_HIGHLEVEL0	42000	r/w	Sets the window’s upper level relatively to the channel’s input range.	board dependant
SPC_LOWLEVEL0	42100	r/w	Sets the window’s lower level relatively to the channel’s input range.	board dependant
SPC_PULSEWIDTH	44000	r/w	Set to the desired pulsewidth in samples.	2 to 255

(c) Spectrum GmbH

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Spectrum Brands MC.31XX manual Channel window trigger for long inner signals, Channel window trigger for long outer signals

Contents

English version April 27 MC.31xxPage Software Hardware InstallationSoftware Driver Installation Introduction Standard acquisition modes Fifo ModeProgramming the Board Analog Inputs Option Extra I/O Option Multiple RecordingOption Gated Sampling Option Timestamp Preface IntroductionPreface General Information Different models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Introduction Additional options Additional optionsDigital inputs Extra I/O Option -XMF Timestamp Starhub Spectrum type plate Hardware information Block diagram Technical Data Order No Description Dynamic ParametersOrder information IntroductionHardware information Hardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Only use the included flat ribbon cables Installing multiple boards synchronized by starhubMounting the wired boards Hooking up the boards Installing multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Version control InstallationSoftware Driver Installation Windows Windows Driver Update Windows Driver Update Windows XP Software Driver Installation Windows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Overview Linux Automatic load of the driver Installing the deviceNow it is possible to access the board using this device Driver info Software Overview SoftwareSoftware Overview First Test with SBench Borland C++ Builder ++ Driver InterfaceHeader files Microsoft Visual C++ Include Drivers Other Windows C/C++ compilersNational Instruments LabWindows/CVI Driver functions Function SpcSetData Windows Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetParam Examples Delphi Pascal Programming InterfaceType definition Include Driver Software Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Register tables Error handlingProgramming the Board Overview PCI Register Example for error checkingInitialization Starting the automatic initialization routine Date of production Installed memoryInstalled features and options Hardware version Driver version Used interrupt lineUsed type of driver Programming the Board Initialization Spcpciserialno Powerdown and resetExample program for the board initialization Spcpcimemsize Analog Inputs Analog InputsChannel Selection Important note on channels selection SPCCHROUTE1 Channel reroutingRerouting information for module SPCCHROUTE0 Input ranges Setting up the inputs Register Value Direction Description Offset range Input offset Automatical adjustment of the offset settings Overrange bitInput termination Spcadjsave ADJUSER0 Spcadjautoadj Adjall Pretrigger = memsize posttrigger Standard acquisition modesProgramming Memory, Pre- and Posttrigger Minimum memsize and posttrigger in samples Starting without interrupt classic modeCommand register Maximum posttrigger in MSamples Starting with interrupt driven mode Standard acquisition modes ProgrammingStatus register Data organization Normal modeFast 8 bit mode 201100 Enables the fast 8 bit mode Value ’len’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’start’ as a 32 bit integer value Programming Speed Limitations Fifo ModeGeneral Information Background Fifo Read 60040 Read out the number of available Fifo buffers Programming Fifo ModeSoftware Buffers Theoretical maximum sample rate PCI Bus Throughput Digital I/O 701x or 702x or pattern generator boards Fifo Mode ProgrammingBuffer processing Analog acquisition or generation boards Spcfifowait Example Fifo acquisition modeFifo acquisition example Spcfifostart Sample format Clock generation Internally generated sample rateStandard internal sample rate Clock generation Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode External reference clock Maximum external samplerate in MS/s External clockingDirect external clock Minimum external sample rate External clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo External TTL trigger Trigger modes and appendant registersGeneral Description Software trigger Positive TTL trigger Example on how to set up the board for positive TTL triggerEdge triggers Trigger modes and appendant registers TTL pulsewidth trigger for short High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for long High pulses Spcpulsewidth TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses Spctriggermode Tmttlhighlp Tmchxoff Channel TriggerOverview of the channel trigger registers Spctriggermode Tmchannel SPCTRIGGERMODE2 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE0 Tmchxoff Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mV Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos SPCHIGHLEVEL0 Channel trigger on positive and negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on negative edge Channel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat negative pulses Channel steepness trigger for flat positive pulses Channel steepness trigger for steep negative pulses Channel steepness trigger for steep positive pulses Channel window trigger for leaving signals Channel window trigger for entering signals Channel window trigger for long outer signals Channel window trigger for long inner signals Channel window trigger for short outer signals Channel window trigger for short inner signals Recording modes Standard ModeWhen using Multiple Recording pretrigger is not available Option Multiple Recording Spctriggermode Resulting start delaysTrigger modesOption Multiple Recording Spcmemsize Spcgate General information and trigger delayOption Gated Sampling Option Gated Sampling Alignement samples per channel End of gate alignement External TTL edge trigger Number of samples on gate signalAllowed trigger modes Option Gated SamplingTrigger modes Spctriggermode Tmttlpos Example programExample program Option Gated Sampling Channel trigger Limits StartReset modeOption Timestamp Timestamp modes Reading out timestamp data RefClock mode optionalFunctions for accessing the data Timestamp Status Data format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Channel direction Option Extra I/ODigital I/Os Analog Outputs Programming example Option Extra I/O Programming example Spcreaddigital Bit Standard Mode Digital Inputs enabledOption Digital inputs Sample format Synchronization with option starhub Synchronization OptionDifferent synchronization options Synchronization with option cascading Write Data to on-board memory output boards only Setup order for the different synchronization optionsSet up the board parameters Let the master calculate it’s clocking 4a Define synchronization or trigger Example for data writingDefine the boards for trigger master Example of board #2 set as trigger master Arm the boards for synchronization Define the board for clock masterExample board number 0 is clock master Define the remaining boards as clock slaves Restarting the board for another synchronized run Start all of the trigger master boardsWait for the end of the measurement Read data from the on-board memory acquisition boards only Spcsyncslavefifo Example of Fifo buffer allocation2a Write first data for output boards Spcsyncmasterfifo General information Additions for synchronizing different boards 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Calculating the clock dividers Board type 3025 3131 Setting up the clock dividerBoard type 3122 3120 40 MS/s Additions for equal boards with different sample rates Resulting delays using different boards or speedsDelay in standard non Fifo modes Delay in Fifo mode Appendix Error CodesError Codes Error name Value hex Value dec Error description Pin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable