Pin assignment of the multipin cable

The 40 lead multipin cable is used for the additional digital inputs (on analog acquisition boards only) or additional digital outputs (on analog generation boards only) as well as for the digital I/O or pat- tern generator boards.

The flat ribbon cable is shipped with the boards that are equipped with one or more of the above mentioned options. The cable ends are assembled with a standard IDC socket connector so you can eas- ily make connections to your type of equipment or DUT (device under test).

The pin assignment is given in the table in the according chapter of the appendix.

102	MC.31xx Manual

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Image 102

Spectrum Brands MC.31XX manual Pin assignment of the multipin cable

Contents

MC.31xx English version April 27Page Introduction Hardware InstallationSoftware Driver Installation Software Analog Inputs Fifo ModeProgramming the Board Standard acquisition modes Option Timestamp Option Multiple RecordingOption Gated Sampling Option Extra I/O General Information IntroductionPreface Preface Different models of the MC.31xx series MC.3110 MC.3120 MC.3130 MC.3111 MC.3121 MC.3131Introduction MC.3112 MC.3122 MC.3132 Extra I/O Option -XMF Additional optionsDigital inputs Introduction Additional options Starhub Timestamp Spectrum type plate Block diagram Technical Data Hardware information IntroductionHardware information Dynamic ParametersOrder information Order No Description Hardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMFHardware Installation Hooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cables Installing multiple synchronized boards Software Driver Installation Interrupt SharingInterrupt Sharing Windows InstallationSoftware Driver Installation Windows Version control Driver Update Windows Driver Update Software Driver Installation Windows XP Windows XP Software Driver Installation Windows NT Windows NTAdding boards to the Windows NT driver Linux Overview Driver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driver First Test with SBench SoftwareSoftware Overview Software Overview Microsoft Visual C++ ++ Driver InterfaceHeader files Borland C++ Builder Driver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include Drivers Function SpcSetParam Software ++ Driver Interface Using the Driver under LinuxFunction SpcSetParam Function SpcSetData Windows Include Driver Delphi Pascal Programming InterfaceType definition Examples Software Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tables Starting the automatic initialization routine Example for error checkingInitialization PCI Register Hardware version Installed memoryInstalled features and options Date of production Programming the Board Initialization Used interrupt lineUsed type of driver Driver version Spcpcimemsize Powerdown and resetExample program for the board initialization Spcpciserialno Important note on channels selection Analog InputsChannel Selection Analog Inputs SPCCHROUTE0 Channel reroutingRerouting information for module SPCCHROUTE1 Setting up the inputs Input ranges Input offset Register Value Direction Description Offset range Automatical adjustment of the offset settings Overrange bitInput termination Spcadjautoadj Adjall Spcadjsave ADJUSER0 Memory, Pre- and Posttrigger Standard acquisition modesProgramming Pretrigger = memsize posttrigger Maximum posttrigger in MSamples Starting without interrupt classic modeCommand register Minimum memsize and posttrigger in samples Starting with interrupt driven mode Standard acquisition modes ProgrammingStatus register 201100 Enables the fast 8 bit mode Normal modeFast 8 bit mode Data organization Value ’start’ as a 32 bit integer value Standard modeReading out the data with SpcGetData Value ’len’ as a 32 bit integer value Programming Background Fifo Read Fifo ModeGeneral Information Speed Limitations Theoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffers Analog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boards Spcfifostart Example Fifo acquisition modeFifo acquisition example Spcfifowait Sample format Clock generation Internally generated sample rateStandard internal sample rate External reference clock Using plain quartz without PLLMaximum internal sample rate in MS/s normal mode Clock generation Minimum external sample rate External clockingDirect external clock Maximum external samplerate in MS/s External clock with divider CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3Fifo Software trigger Trigger modes and appendant registersGeneral Description External TTL trigger Trigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL trigger TTL pulsewidth trigger for long High pulses Pulsewidth triggersPositive and negative TTL trigger TTL pulsewidth trigger for short High pulses Spctriggermode Tmttlhighlp TTL pulsewidth trigger for long LOW pulsesTTL pulsewidth trigger for short LOW pulses Spcpulsewidth Spctriggermode Tmchannel Channel TriggerOverview of the channel trigger registers Tmchxoff SPCTRIGGERMODE0 Tmchxoff TriggerlevelSpctriggermode Tmchor SPCTRIGGERMODE2 Tmchxoff SPCHIGHLEVEL0 Reading out the number of possible trigger levelsSPCTRIGGERMODE0 Tmchxpos Input ranges Triggerlevel ±50 mV ±100 mV ±200 mV ±500 mV Channel trigger on negative edge Detailed description of the channel trigger modesChannel trigger on positive edge Channel trigger on positive and negative edge Channel pulsewidth trigger for long positive pulses Channel pulsewidth trigger for long negative pulses Channel pulsewidth trigger for short positive pulses Channel pulsewidth trigger for short negative pulsesTmchxposgsp Channel steepness trigger for flat positive pulses Channel steepness trigger for flat negative pulses Channel steepness trigger for steep positive pulses Channel steepness trigger for steep negative pulses Channel window trigger for entering signals Channel window trigger for leaving signals Channel window trigger for long inner signals Channel window trigger for long outer signals Channel window trigger for short inner signals Channel window trigger for short outer signals Option Multiple Recording Standard ModeWhen using Multiple Recording pretrigger is not available Recording modes Spcmemsize Resulting start delaysTrigger modesOption Multiple Recording Spctriggermode Option Gated Sampling General information and trigger delayOption Gated Sampling Spcgate End of gate alignement Alignement samples per channel Option Gated SamplingTrigger modes Number of samples on gate signalAllowed trigger modes External TTL edge trigger Channel trigger Example programExample program Option Gated Sampling Spctriggermode Tmttlpos Timestamp modes StartReset modeOption Timestamp Limits Timestamp Status RefClock mode optionalFunctions for accessing the data Reading out timestamp data Data format SpcGetData nr, ch, start, len, dataSpctimestampcount Standard acquisition mode Example programsAcquisition with Multiple Recording Analog Outputs Option Extra I/ODigital I/Os Channel direction Programming example Programming example Option Extra I/O Sample format Bit Standard Mode Digital Inputs enabledOption Digital inputs Spcreaddigital Synchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhub Let the master calculate it’s clocking Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards only Example of board #2 set as trigger master Example for data writingDefine the boards for trigger master 4a Define synchronization or trigger Define the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronization Read data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Restarting the board for another synchronized run Spcsyncmasterfifo Example of Fifo buffer allocation2a Write first data for output boards Spcsyncslavefifo Additions for synchronizing different boards General information Calculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx 40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131 Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample rates Error name Value hex Value dec Error description Error CodesError Codes Appendix Pin assignment of the multipin connector Extra I/O with external connectorOption -XMFOption Digital inputs Pin assignment of the multipin cable