Intel 830 manual Pwrgood Input and TAP Signal Group DC Specifications

Electrical Specifications

Table 2-12. PWRGOOD Input and TAP Signal Group DC Specifications

Symbol	Parameter	Min	Max	Unit	Notes1, 2
VHYS	Input Hysteresis	200	350	mV	3
VT+	Input low to high	0.5 * (VTT + VHYS_MIN)	0.5 * (VTT + VHYS_MAX)	V	4
	threshold voltage
VT-	Input high to low	0.5 * (VTT – VHYS_MAX)	0.5 * (VTT – VHYS_MIN)	V	4
	threshold voltage
VOH	Output High Voltage	N/A	VTT	V	4
IOL	Output Low Current	-	45	mA	5
ILI	Input Leakage Current	-	± 200	µA	6
ILO	Output Leakage	-	± 200	µA	6
	Current
RON	Buffer On Resistance	7	12	Ω

NOTES:

1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.All outputs are open drain.

3.VHYS represents the amount of hysteresis, nominally centered about 0.5 * VTT, for all TAP inputs.

4.The VTT referred to in these specifications refers to instantaneous VTT.

5.The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load.

6.Leakage to VSS with land held at VTT.

Table 2-13. GTL+ Asynchronous Signal Group DC Specifications

Symbol	Parameter	Min	Max	Unit	Notes1
VIL	Input Low Voltage	0.0	VTT/2 – (0.10 * VTT)	-	2,	3
VIH	Input High Voltage	VTT/2 + (0.10 * VTT)	VTT	-	3, 4, 5, 6
VOH	Output High Voltage	0.90*VTT	VTT	V	5, 6, 7
IOL	Output Low Current	—	VTT/[(0.50*RTT_MIN) +	A	8
			RON_MIN]
ILI	Input Leakage Current	N/A	± 200	µA	9
ILO	Output Leakage	N/A	± 200	µA	10
	Current
RON	Buffer On Resistance	8	12	Ω
NOTES:

1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3.LINT0/INTR, LINT1/NMI, and FORCEPR# use GTLREF as a reference voltage. For these two signals, VIH = GTLREF + (0.10 * VTT) and VIL= GTLREF – (0.10 * VTT).

4.VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5.VIH and VOH may experience excursions above VTT.

6.The VTT referred to in these specifications refers to instantaneous VTT.

7.All outputs are open drain.

8.The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load.

9.Leakage to VSS with land held at VTT.

10.Leakage to VTT with land held at 300 mV.

30 Datasheet