Intel 830 manual N30

Page 60

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

Land Name

Signal Buffer

Direction

#

Type

 

 

 

 

 

 

N30

VCC

Power/Other

 

 

 

 

 

P1

TESTHI11

Power/Other

Input

 

 

 

 

P2

SMI#

Asynch GTL+

Input

 

 

 

 

P3

INIT#

Asynch GTL+

Input

 

 

 

 

P4

VSS

Power/Other

 

 

 

 

 

P5

RESERVED

 

 

 

 

 

 

P6

A4#

Source Synch

Input/Output

 

 

 

 

P7

VSS

Power/Other

 

 

 

 

 

P8

VCC

Power/Other

 

 

 

 

 

P23

VSS

Power/Other

 

 

 

 

 

P24

VSS

Power/Other

 

 

 

 

 

P25

VSS

Power/Other

 

 

 

 

 

P26

VSS

Power/Other

 

 

 

 

 

P27

VSS

Power/Other

 

 

 

 

 

P28

VSS

Power/Other

 

 

 

 

 

P29

VSS

Power/Other

 

 

 

 

 

P30

VSS

Power/Other

 

 

 

 

 

R1

COMP3

Power/Other

Input

 

 

 

 

R2

VSS

Power/Other

 

 

 

 

 

R3

FERR#/PBE#

Asynch GTL+

Output

 

 

 

 

R4

A8#

Source Synch

Input/Output

 

 

 

 

R5

VSS

Power/Other

 

 

 

 

 

R6

ADSTB0#

Source Synch

Input/Output

 

 

 

 

R7

VSS

Power/Other

 

 

 

 

 

R8

VCC

Power/Other

 

 

 

 

 

R23

VSS

Power/Other

 

 

 

 

 

R24

VSS

Power/Other

 

 

 

 

 

R25

VSS

Power/Other

 

 

 

 

 

R26

VSS

Power/Other

 

 

 

 

 

R27

VSS

Power/Other

 

 

 

 

 

R28

VSS

Power/Other

 

 

 

 

 

R29

VSS

Power/Other

 

 

 

 

 

R30

VSS

Power/Other

 

 

 

 

 

T1

COMP1

Power/Other

Input

 

 

 

 

T2

FC4

Power/Other

Input

 

 

 

 

T3

VSS

Power/Other

 

 

 

 

 

T4

A11#

Source Synch

Input/Output

 

 

 

 

T5

A9#

Source Synch

Input/Output

 

 

 

 

T6

VSS

Power/Other

 

 

 

 

 

T7

VSS

Power/Other

 

 

 

 

 

T8

VCC

Power/Other

 

 

 

 

 

Table 4-2. Numerical Land Assignment

Land

Land Name

Signal Buffer

Direction

#

Type

 

 

 

 

 

 

T23

VCC

Power/Other

 

 

 

 

 

T24

VCC

Power/Other

 

 

 

 

 

T25

VCC

Power/Other

 

 

 

 

 

T26

VCC

Power/Other

 

 

 

 

 

T27

VCC

Power/Other

 

 

 

 

 

T28

VCC

Power/Other

 

 

 

 

 

T29

VCC

Power/Other

 

 

 

 

 

T30

VCC

Power/Other

 

 

 

 

 

U1

VSS

Power/Other

 

 

 

 

 

U2

AP0#

Common Clock

Input/Output

 

 

 

 

U3

AP1#

Common Clock

Input/Output

 

 

 

 

U4

A13#

Source Synch

Input/Output

 

 

 

 

U5

A12#

Source Synch

Input/Output

 

 

 

 

U6

A10#

Source Synch

Input/Output

 

 

 

 

U7

VSS

Power/Other

 

 

 

 

 

U8

VCC

Power/Other

 

 

 

 

 

U23

VCC

Power/Other

 

 

 

 

 

U24

VCC

Power/Other

 

 

 

 

 

U25

VCC

Power/Other

 

 

 

 

 

U26

VCC

Power/Other

 

 

 

 

 

U27

VCC

Power/Other

 

 

 

 

 

U28

VCC

Power/Other

 

 

 

 

 

U29

VCC

Power/Other

 

 

 

 

 

U30

VCC

Power/Other

 

 

 

 

 

V1

MSID1

Power/Other

Input

 

 

 

 

V2

LL_ID0

Power/Other

Output

 

 

 

 

V3

VSS

Power/Other

 

 

 

 

 

V4

A15#

Source Synch

Input/Output

 

 

 

 

V5

A14#

Source Synch

Input/Output

 

 

 

 

V6

VSS

Power/Other

 

 

 

 

 

V7

VSS

Power/Other

 

 

 

 

 

V8

VCC

Power/Other

 

 

 

 

 

V23

VSS

Power/Other

 

 

 

 

 

V24

VSS

Power/Other

 

 

 

 

 

V25

VSS

Power/Other

 

 

 

 

 

V26

VSS

Power/Other

 

 

 

 

 

V27

VSS

Power/Other

 

 

 

 

 

V28

VSS

Power/Other

 

 

 

 

 

V29

VSS

Power/Other

 

 

 

 

 

V30

VSS

Power/Other

 

 

 

 

 

W1

MSID0

Power/Other

Input

 

 

 

 

60

Datasheet

Image 60
Contents Datasheet Intel Pentium D Processor 800Δ SequenceContents Contents Halt and Enhanced Halt Powerdown States Figures Tables Revision History Revision Description DateInitial release May Contents Intel Pentium D Processor 800 Sequence Features Contents Introduction Terminology Processor Packaging TerminologyReferences ReferencesIntroduction Electrical Specifications Power and Ground LandsDecoupling Guidelines VCC DecouplingVoltage Identification FSB DecouplingVoltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0Reserved, Unused, FC and Testhi Signals Voltage and Current Specifications DC Voltage and Current SpecificationsSymbol Parameter Min Max Unit Absolute Maximum and Minimum RatingsVoltage and Current Specifications Symbol Parameter Min Typ Max UnitVID Vttout ICCIcc a Voltage Deviation from VID Setting V 1, 2 000065 072Icc a 000 019 007 026013 033 020 040Icc a VCC Overshoot Specification VCC Overshoot SpecificationsMagnitude of V CC overshoot above VID 050 Time duration of V CC overshoot above VIDSignaling Specifications FSB Signal GroupsDie Voltage Validation FSB Signal Groups Signal GroupSignals Signals Associated Strobe2 GTL+ Asynchronous Signals Signal CharacteristicsSignal Reference Voltages FSB DC Specifications 10. BSEL20 and VID50 Signal Group DC Specifications11. GTL+ Signal Group DC Specifications Symbol Parameter Max Unit12. Pwrgood Input and TAP Signal Group DC Specifications 13. GTL+ Asynchronous Signal Group DC Specifications14. Vttpwrgd DC Specifications 15. Bootselect and MSID10 DC SpecificationsSymbol Parameter Min Typ Max Units 16. GTL+ Bus Voltage DefinitionsClock Specifications FSB Frequency Select Signals17. Core Frequency to FSB Multiplier Configuration FSB Clock BCLK10 and Processor ClockingPhase Lock Loop PLL and Filter 18. BSEL20 Frequency Table for BCLK10FSB Frequency 133 MHzPhase Lock Loop PLL Filter Requirements Package Mechanical Specifications Package Mechanical DrawingProcessor Package Drawing Package Mechanical Specifications Package Mechanical Specifications Package Loading Specifications Processor Loading SpecificationsProcessor Component Keep-Out Zones Package Handling GuidelinesPackage Insertion Specifications Processor Mass SpecificationProcessor Materials Processor MarkingsProcessor Top-Side Marking Example Intel Pentium D Processor Processor Land Coordinates Processor Land Coordinates, Top ViewLand Listing and Signal Descriptions Processor Land AssignmentsLandout Diagram Top View Left Side Landout Diagram Top View Right Side Land Name Signal Buffer Direction Type Alphabetical Land AssignmentsDBI0# GTLREF1 VCC AC8 VCC AK8 Vccmb AN5 VSS AA3 VSS AJ4 E11 Power/Other Vssmb AN6 Land Land Name Signal Buffer Direction Type Numerical Land AssignmentReserved ADS# Reserved DEFER# J12 N30 AA1 Vttoutright AD4 VSS AH1 VSS AK2 VSS AN1 VSS Alphabetical Signals Reference Signal Description Sheet 1Request Signals Name Type DescriptionSignal Description Sheet 2 NameSignal Description Sheet 3 Bus Signal Data Bus SignalsData Group Signal Description Sheet 4 Signal Description Sheet 5 Signal Description Sheet 6 RESET#Pwrgood Signal Description Sheet 7 Signal Description Sheet 8 Land Listing and Signal Descriptions Thermal Specifications and Design Considerations Processor Thermal SpecificationsThermal Specifications Processor Thermal Specifications Minimum Maximum T C CGHz Power Maximum T C Thermal Profile for the Pentium D Processor with PRB=1Power Thermal Profile for the Pentium D Processor with PRB=0Processor Thermal Features Thermal MetrologyThermal Monitor On-Demand Mode PROCHOT# SignalFORCEPR# Signal Pin THERMTRIP# Signal Tcontrol and Fan Speed ReductionThermal Diode Thermal Diode ParametersSignal Name Land Number Signal Description Thermal Diode InterfaceDiode anode Thermal Specifications and Design Considerations Features Power-On Configuration OptionsClock Control and Low Power States Power-On Configuration Option SignalsHalt and Enhanced Halt Powerdown States Normal StateEnhanced Halt Powerdown State Stop-Grant StateEnhanced Halt Snoop or Halt Snoop State, Grant Snoop State Enhanced Intel SpeedStep TechnologyBoxed Processor Specifications Mechanical Representation of the Boxed ProcessorMechanical Specifications Boxed Processor Cooling Solution DimensionsBoxed Processor Fan Heatsink Weight Fan Heatsink Power SupplyElectrical Requirements Fan Heatsink Power and Signal Specifications +12 V 12 volt fan power supplyDescription Min Typ Max Unit Sense frequencyThermal Specifications Boxed Processor Cooling RequirementsBoxed Processor Specifications Variable Speed Fan Boxed Processor Fan Boxed Processor Fan SpeedFan operates at its highest speed Boxed Processor Specifications Mechanical Representation of the Boxed Processor Cooling Solution Dimensions Assembly Stack Including the Support and Retention Module Boxed Processor Support and Retention Module SRMSense Sense frequency ControlDatasheet 101 Boxed Processor TMA Set Points Boxed Processor Boxed Processor Fan SpeedDatasheet 103 104 Debug Tools Specifications Logic Analyzer Interface LAIMechanical Considerations Electrical Considerations106

830 specifications

The Intel 830 chipset, introduced in the early 2000s, marked a significant evolution in Intel's chipset architecture for desktop and mobile computing. Known for its support of the Pentium 4 processors, the 830 chipset was tailored for both performance and stability, making it an appealing choice for OEMs and enthusiasts alike.

One of the standout features of the Intel 830 chipset is its support for DDR SDRAM, providing a much-needed boost in memory bandwidth compared to its predecessors. With dual-channel memory support, the chipset could utilize two memory modules simultaneously, which effectively doubled the data transfer rate and enhanced overall system performance. This made the Intel 830 particularly beneficial for applications requiring high memory throughput, such as multimedia processing and gaming.

Another important characteristic of the Intel 830 was its integrated graphics support, featuring Intel's Extreme Graphics technology. This integration allowed for decent graphics performance without the need for a dedicated GPU, making it suitable for budget systems and everyday computing tasks. However, for power users and gaming enthusiasts, the option to incorporate a discrete graphics card remained available through the provided PCI Express x16 slot.

The Intel 830 chipset also boasted advanced I/O capabilities, including support for USB 2.0, which provided faster data transfer rates compared to USB 1.1, and enhanced IDE interfaces for connecting hard drives and optical devices. With its Hyper-Threading technology support, the chipset allowed for improved multitasking efficiency, enabling a single processor to execute multiple threads simultaneously, a feature that was particularly beneficial in server environments and complex computing tasks.

In terms of connectivity, the Intel 830 supported multiple bus interfaces, including PCI Express and AGP, thereby enabling users to expand their systems with various add-on cards. This flexibility contributed to the chipset's longevity in the marketplace, as it catered to a wide range of user needs from light computing to intensive gaming and content creation.

In summary, the Intel 830 chipset combined enhanced memory capabilities, integrated graphics performance, robust I/O features, and flexible expansion options, making it a versatile choice for various computing environments during its time. It played a key role in shaping the landscape of early 2000s computing, paving the way for future advancements in chipset technology. Its legacy continues to influence modern computing architectures, illustrating the lasting impact of Intel’s innovative design principles.