Intel 830 manual DBI0#

Page 47

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

Land

Signal Buffer

Direction

#

Type

 

 

 

 

 

 

D21#

E10

Source Synch

Input/Output

 

 

 

 

D22#

D10

Source Synch

Input/Output

 

 

 

 

D23#

F11

Source Synch

Input/Output

 

 

 

 

D24#

F12

Source Synch

Input/Output

 

 

 

 

D25#

D13

Source Synch

Input/Output

 

 

 

 

D26#

E13

Source Synch

Input/Output

 

 

 

 

D27#

G13

Source Synch

Input/Output

 

 

 

 

D28#

F14

Source Synch

Input/Output

 

 

 

 

D29#

G14

Source Synch

Input/Output

 

 

 

 

D30#

F15

Source Synch

Input/Output

 

 

 

 

D31#

G15

Source Synch

Input/Output

 

 

 

 

D32#

G16

Source Synch

Input/Output

 

 

 

 

D33#

E15

Source Synch

Input/Output

 

 

 

 

D34#

E16

Source Synch

Input/Output

 

 

 

 

D35#

G18

Source Synch

Input/Output

 

 

 

 

D36#

G17

Source Synch

Input/Output

 

 

 

 

D37#

F17

Source Synch

Input/Output

 

 

 

 

D38#

F18

Source Synch

Input/Output

 

 

 

 

D39#

E18

Source Synch

Input/Output

 

 

 

 

D40#

E19

Source Synch

Input/Output

 

 

 

 

D41#

F20

Source Synch

Input/Output

 

 

 

 

D42#

E21

Source Synch

Input/Output

 

 

 

 

D43#

F21

Source Synch

Input/Output

 

 

 

 

D44#

G21

Source Synch

Input/Output

 

 

 

 

D45#

E22

Source Synch

Input/Output

 

 

 

 

D46#

D22

Source Synch

Input/Output

 

 

 

 

D47#

G22

Source Synch

Input/Output

 

 

 

 

D48#

D20

Source Synch

Input/Output

 

 

 

 

D49#

D17

Source Synch

Input/Output

 

 

 

 

D50#

A14

Source Synch

Input/Output

 

 

 

 

D51#

C15

Source Synch

Input/Output

 

 

 

 

D52#

C14

Source Synch

Input/Output

 

 

 

 

D53#

B15

Source Synch

Input/Output

 

 

 

 

D54#

C18

Source Synch

Input/Output

 

 

 

 

D55#

B16

Source Synch

Input/Output

 

 

 

 

D56#

A17

Source Synch

Input/Output

 

 

 

 

D57#

B18

Source Synch

Input/Output

 

 

 

 

D58#

C21

Source Synch

Input/Output

 

 

 

 

D59#

B21

Source Synch

Input/Output

 

 

 

 

D60#

B19

Source Synch

Input/Output

 

 

 

 

Table 4-1. Alphabetical Land

Assignments

Land Name

Land

Signal Buffer

Direction

#

Type

 

 

 

 

 

 

D61#

A19

Source Synch

Input/Output

 

 

 

 

D62#

A22

Source Synch

Input/Output

 

 

 

 

D63#

B22

Source Synch

Input/Output

 

 

 

 

DBI0#

A8

Source Synch

Input/Output

 

 

 

 

DBI1#

G11

Source Synch

Input/Output

 

 

 

 

DBI2#

D19

Source Synch

Input/Output

 

 

 

 

DBI3#

C20

Source Synch

Input/Output

 

 

 

 

DBR#

AC2

Power/Other

Output

 

 

 

 

DBSY#

B2

Common Clock

Input/Output

 

 

 

 

DEFER#

G7

Common Clock

Input

 

 

 

 

DP0#

J16

Common Clock

Input/Output

 

 

 

 

DP1#

H15

Common Clock

Input/Output

 

 

 

 

DP2#

H16

Common Clock

Input/Output

 

 

 

 

DP3#

J17

Common Clock

Input/Output

 

 

 

 

DRDY#

C1

Common Clock

Input/Output

 

 

 

 

DSTBN0#

C8

Source Synch

Input/Output

 

 

 

 

DSTBN1#

G12

Source Synch

Input/Output

 

 

 

 

DSTBN2#

G20

Source Synch

Input/Output

 

 

 

 

DSTBN3#

A16

Source Synch

Input/Output

 

 

 

 

DSTBP0#

B9

Source Synch

Input/Output

 

 

 

 

DSTBP1#

E12

Source Synch

Input/Output

 

 

 

 

DSTBP2#

G19

Source Synch

Input/Output

 

 

 

 

DSTBP3#

C17

Source Synch

Input/Output

 

 

 

 

FC3

J2

Power/Other

Input

 

 

 

 

FC4

T2

Power/Other

Input

 

 

 

 

FC5

F2

Common Clock

Input

 

 

 

 

FC7

G5

Source Synch

Output

 

 

 

 

FC10

E24

Power/Other

Input

 

 

 

 

FC11

AM5

Power/Other

Output

 

 

 

 

FC12

AM7

Power/Other

Output

 

 

 

 

FC16

AN7

Power/Other

Output

 

 

 

 

FC17

Y3

Power/Other

Input

 

 

 

 

FC18

AE3

Power/Other

Input

 

 

 

 

FC19

B13

Power/Other

Input

 

 

 

 

FC20

E5

Power/Other

Input

 

 

 

 

FC22

J3

Power/Other

Input

 

 

 

 

FERR#/PBE#

R3

Asynch GTL+

Output

 

 

 

 

FORCEPR#

AK6

Asynch GTL+

Input

 

 

 

 

GTLREF_SEL

H29

Power/Other

Output

 

 

 

 

GTLREF0

H1

Power/Other

Input

 

 

 

 

Datasheet

47

Image 47
Contents Intel Pentium D Processor 800Δ Sequence DatasheetContents Contents Halt and Enhanced Halt Powerdown States Figures Tables Initial release May Revision HistoryRevision Description Date Contents Intel Pentium D Processor 800 Sequence Features Contents Introduction Processor Packaging Terminology TerminologyReferences ReferencesIntroduction VCC Decoupling Electrical SpecificationsPower and Ground Lands Decoupling GuidelinesFSB Decoupling Voltage IdentificationVID5 VID4 VID3 VID2 VID1 VID0 Voltage Identification DefinitionReserved, Unused, FC and Testhi Signals Absolute Maximum and Minimum Ratings Voltage and Current SpecificationsDC Voltage and Current Specifications Symbol Parameter Min Max UnitVttout ICC Voltage and Current SpecificationsSymbol Parameter Min Typ Max Unit VID072 Icc a Voltage Deviation from VID Setting V 1, 2000 065Icc a 020 040 000 019007 026 013 033Icc a Time duration of V CC overshoot above VID VCC Overshoot SpecificationVCC Overshoot Specifications Magnitude of V CC overshoot above VID 050Die Voltage Validation Signaling SpecificationsFSB Signal Groups Signals Associated Strobe FSB Signal GroupsSignal Group SignalsSignal Reference Voltages 2 GTL+ Asynchronous SignalsSignal Characteristics Symbol Parameter Max Unit FSB DC Specifications10. BSEL20 and VID50 Signal Group DC Specifications 11. GTL+ Signal Group DC Specifications13. GTL+ Asynchronous Signal Group DC Specifications 12. Pwrgood Input and TAP Signal Group DC Specifications16. GTL+ Bus Voltage Definitions 14. Vttpwrgd DC Specifications15. Bootselect and MSID10 DC Specifications Symbol Parameter Min Typ Max UnitsFSB Clock BCLK10 and Processor Clocking Clock SpecificationsFSB Frequency Select Signals 17. Core Frequency to FSB Multiplier Configuration133 MHz Phase Lock Loop PLL and Filter18. BSEL20 Frequency Table for BCLK10 FSB FrequencyPhase Lock Loop PLL Filter Requirements Package Mechanical Drawing Package Mechanical SpecificationsProcessor Package Drawing Package Mechanical Specifications Package Mechanical Specifications Package Handling Guidelines Package Loading SpecificationsProcessor Loading Specifications Processor Component Keep-Out ZonesProcessor Markings Package Insertion SpecificationsProcessor Mass Specification Processor MaterialsProcessor Top-Side Marking Example Intel Pentium D Processor Processor Land Coordinates, Top View Processor Land CoordinatesProcessor Land Assignments Land Listing and Signal DescriptionsLandout Diagram Top View Left Side Landout Diagram Top View Right Side Alphabetical Land Assignments Land Name Signal Buffer Direction TypeDBI0# GTLREF1 VCC AC8 VCC AK8 Vccmb AN5 VSS AA3 VSS AJ4 E11 Power/Other Vssmb AN6 Numerical Land Assignment Land Land Name Signal Buffer Direction TypeReserved ADS# Reserved DEFER# J12 N30 AA1 Vttoutright AD4 VSS AH1 VSS AK2 VSS AN1 VSS Name Type Description Alphabetical Signals ReferenceSignal Description Sheet 1 Request SignalsName Signal Description Sheet 2Data Group Signal Description Sheet 3Bus Signal Data Bus Signals Signal Description Sheet 4 Signal Description Sheet 5 Pwrgood Signal Description Sheet 6RESET# Signal Description Sheet 7 Signal Description Sheet 8 Land Listing and Signal Descriptions Thermal Specifications Thermal Specifications and Design ConsiderationsProcessor Thermal Specifications GHz Processor Thermal SpecificationsMinimum Maximum T C C Thermal Profile for the Pentium D Processor with PRB=1 Power Maximum T CThermal Profile for the Pentium D Processor with PRB=0 PowerThermal Monitor Processor Thermal FeaturesThermal Metrology PROCHOT# Signal On-Demand ModeFORCEPR# Signal Pin Thermal Diode Parameters THERMTRIP# SignalTcontrol and Fan Speed Reduction Thermal DiodeDiode anode Signal Name Land Number Signal DescriptionThermal Diode Interface Thermal Specifications and Design Considerations Power-On Configuration Option Signals FeaturesPower-On Configuration Options Clock Control and Low Power StatesNormal State Halt and Enhanced Halt Powerdown StatesStop-Grant State Enhanced Halt Powerdown StateEnhanced Intel SpeedStep Technology Enhanced Halt Snoop or Halt Snoop State, Grant Snoop StateMechanical Representation of the Boxed Processor Boxed Processor SpecificationsBoxed Processor Cooling Solution Dimensions Mechanical SpecificationsElectrical Requirements Boxed Processor Fan Heatsink WeightFan Heatsink Power Supply Sense frequency Fan Heatsink Power and Signal Specifications+12 V 12 volt fan power supply Description Min Typ Max UnitBoxed Processor Cooling Requirements Thermal SpecificationsBoxed Processor Specifications Fan operates at its highest speed Variable Speed FanBoxed Processor Fan Boxed Processor Fan Speed Boxed Processor Specifications Mechanical Representation of the Boxed Processor Cooling Solution Dimensions Boxed Processor Support and Retention Module SRM Assembly Stack Including the Support and Retention ModuleControl Sense Sense frequencyDatasheet 101 Boxed Processor Boxed Processor Fan Speed Boxed Processor TMA Set PointsDatasheet 103 104 Electrical Considerations Debug Tools SpecificationsLogic Analyzer Interface LAI Mechanical Considerations106

830 specifications

The Intel 830 chipset, introduced in the early 2000s, marked a significant evolution in Intel's chipset architecture for desktop and mobile computing. Known for its support of the Pentium 4 processors, the 830 chipset was tailored for both performance and stability, making it an appealing choice for OEMs and enthusiasts alike.

One of the standout features of the Intel 830 chipset is its support for DDR SDRAM, providing a much-needed boost in memory bandwidth compared to its predecessors. With dual-channel memory support, the chipset could utilize two memory modules simultaneously, which effectively doubled the data transfer rate and enhanced overall system performance. This made the Intel 830 particularly beneficial for applications requiring high memory throughput, such as multimedia processing and gaming.

Another important characteristic of the Intel 830 was its integrated graphics support, featuring Intel's Extreme Graphics technology. This integration allowed for decent graphics performance without the need for a dedicated GPU, making it suitable for budget systems and everyday computing tasks. However, for power users and gaming enthusiasts, the option to incorporate a discrete graphics card remained available through the provided PCI Express x16 slot.

The Intel 830 chipset also boasted advanced I/O capabilities, including support for USB 2.0, which provided faster data transfer rates compared to USB 1.1, and enhanced IDE interfaces for connecting hard drives and optical devices. With its Hyper-Threading technology support, the chipset allowed for improved multitasking efficiency, enabling a single processor to execute multiple threads simultaneously, a feature that was particularly beneficial in server environments and complex computing tasks.

In terms of connectivity, the Intel 830 supported multiple bus interfaces, including PCI Express and AGP, thereby enabling users to expand their systems with various add-on cards. This flexibility contributed to the chipset's longevity in the marketplace, as it catered to a wide range of user needs from light computing to intensive gaming and content creation.

In summary, the Intel 830 chipset combined enhanced memory capabilities, integrated graphics performance, robust I/O features, and flexible expansion options, making it a versatile choice for various computing environments during its time. It played a key role in shaping the landscape of early 2000s computing, paving the way for future advancements in chipset technology. Its legacy continues to influence modern computing architectures, illustrating the lasting impact of Intel’s innovative design principles.