Intel 830 manual Alphabetical Land Assignments, Land Name Signal Buffer Direction Type

Page 46

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

Land

Signal Buffer

Direction

#

Type

 

 

 

 

 

 

A3#

L5

Source Synch

Input/Output

 

 

 

 

A4#

P6

Source Synch

Input/Output

 

 

 

 

A5#

M5

Source Synch

Input/Output

 

 

 

 

A6#

L4

Source Synch

Input/Output

 

 

 

 

A7#

M4

Source Synch

Input/Output

 

 

 

 

A8#

R4

Source Synch

Input/Output

 

 

 

 

A9#

T5

Source Synch

Input/Output

 

 

 

 

A10#

U6

Source Synch

Input/Output

 

 

 

 

A11#

T4

Source Synch

Input/Output

 

 

 

 

A12#

U5

Source Synch

Input/Output

 

 

 

 

A13#

U4

Source Synch

Input/Output

 

 

 

 

A14#

V5

Source Synch

Input/Output

 

 

 

 

A15#

V4

Source Synch

Input/Output

 

 

 

 

A16#

W5

Source Synch

Input/Output

 

 

 

 

A17#

AB6

Source Synch

Input/Output

 

 

 

 

A18#

W6

Source Synch

Input/Output

 

 

 

 

A19#

Y6

Source Synch

Input/Output

 

 

 

 

A20#

Y4

Source Synch

Input/Output

 

 

 

 

A20M#

K3

Asynch GTL+

Input

 

 

 

 

A21#

AA4

Source Synch

Input/Output

 

 

 

 

A22#

AD6

Source Synch

Input/Output

 

 

 

 

A23#

AA5

Source Synch

Input/Output

 

 

 

 

A24#

AB5

Source Synch

Input/Output

 

 

 

 

A25#

AC5

Source Synch

Input/Output

 

 

 

 

A26#

AB4

Source Synch

Input/Output

 

 

 

 

A27#

AF5

Source Synch

Input/Output

 

 

 

 

A28#

AF4

Source Synch

Input/Output

 

 

 

 

A29#

AG6

Source Synch

Input/Output

 

 

 

 

A30#

AG4

Source Synch

Input/Output

 

 

 

 

A31#

AG5

Source Synch

Input/Output

 

 

 

 

A32#

AH4

Source Synch

Input/Output

 

 

 

 

A33#

AH5

Source Synch

Input/Output

 

 

 

 

A34#

AJ5

Source Synch

Input/Output

 

 

 

 

A35#

AJ6

Source Synch

Input/Output

 

 

 

 

ADS#

D2

Common Clock

Input/Output

 

 

 

 

ADSTB0#

R6

Source Synch

Input/Output

 

 

 

 

ADSTB1#

AD5

Source Synch

Input/Output

 

 

 

 

AP0#

U2

Common Clock

Input/Output

 

 

 

 

AP1#

U3

Common Clock

Input/Output

 

 

 

 

BCLK0

F28

Clock

Input

 

 

 

 

Table 4-1. Alphabetical Land

Assignments

Land Name

Land

Signal Buffer

Direction

#

Type

 

 

 

 

 

 

BCLK1

G28

Clock

Input

 

 

 

 

BINIT#

AD3

Common Clock

Input/Output

 

 

 

 

BNR#

C2

Common Clock

Input/Output

 

 

 

 

BOOTSELECT

Y1

Power/Other

Input

 

 

 

 

BPM0#

AJ2

Common Clock

Input/Output

 

 

 

 

BPM1#

AJ1

Common Clock

Input/Output

 

 

 

 

BPM2#

AD2

Common Clock

Input/Output

 

 

 

 

BPM3#

AG2

Common Clock

Input/Output

 

 

 

 

BPM4#

AF2

Common Clock

Input/Output

 

 

 

 

BPM5#

AG3

Common Clock

Input/Output

 

 

 

 

BPRI#

G8

Common Clock

Input

 

 

 

 

BR0#

F3

Common Clock

Input/Output

 

 

 

 

BSEL0

G29

Power/Other

Output

 

 

 

 

BSEL1

H30

Power/Other

Output

 

 

 

 

BSEL2

G30

Power/Other

Output

 

 

 

 

COMP0

A13

Power/Other

Input

 

 

 

 

COMP1

T1

Power/Other

Input

 

 

 

 

COMP2

G2

Power/Other

Input

 

 

 

 

COMP3

R1

Power/Other

Input

 

 

 

 

D0#

B4

Source Synch

Input/Output

 

 

 

 

D1#

C5

Source Synch

Input/Output

 

 

 

 

D2#

A4

Source Synch

Input/Output

 

 

 

 

D3#

C6

Source Synch

Input/Output

 

 

 

 

D4#

A5

Source Synch

Input/Output

 

 

 

 

D5#

B6

Source Synch

Input/Output

 

 

 

 

D6#

B7

Source Synch

Input/Output

 

 

 

 

D7#

A7

Source Synch

Input/Output

 

 

 

 

D8#

A10

Source Synch

Input/Output

 

 

 

 

D9#

A11

Source Synch

Input/Output

 

 

 

 

D10#

B10

Source Synch

Input/Output

 

 

 

 

D11#

C11

Source Synch

Input/Output

 

 

 

 

D12#

D8

Source Synch

Input/Output

 

 

 

 

D13#

B12

Source Synch

Input/Output

 

 

 

 

D14#

C12

Source Synch

Input/Output

 

 

 

 

D15#

D11

Source Synch

Input/Output

 

 

 

 

D16#

G9

Source Synch

Input/Output

 

 

 

 

D17#

F8

Source Synch

Input/Output

 

 

 

 

D18#

F9

Source Synch

Input/Output

 

 

 

 

D19#

E9

Source Synch

Input/Output

 

 

 

 

D20#

D7

Source Synch

Input/Output

 

 

 

 

46

Datasheet

Image 46
Contents Datasheet Intel Pentium D Processor 800Δ SequenceContents Contents Halt and Enhanced Halt Powerdown States Figures Tables Revision Description Date Revision HistoryInitial release May Contents Intel Pentium D Processor 800 Sequence Features Contents Introduction Terminology Processor Packaging TerminologyReferences ReferencesIntroduction Decoupling Guidelines Electrical SpecificationsPower and Ground Lands VCC DecouplingVoltage Identification FSB DecouplingVoltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0Reserved, Unused, FC and Testhi Signals Symbol Parameter Min Max Unit Voltage and Current SpecificationsDC Voltage and Current Specifications Absolute Maximum and Minimum RatingsVID Voltage and Current SpecificationsSymbol Parameter Min Typ Max Unit Vttout ICC065 Icc a Voltage Deviation from VID Setting V 1, 2000 072Icc a 013 033 000 019007 026 020 040Icc a Magnitude of V CC overshoot above VID 050 VCC Overshoot SpecificationVCC Overshoot Specifications Time duration of V CC overshoot above VIDFSB Signal Groups Signaling SpecificationsDie Voltage Validation Signals FSB Signal GroupsSignal Group Signals Associated StrobeSignal Characteristics 2 GTL+ Asynchronous SignalsSignal Reference Voltages 11. GTL+ Signal Group DC Specifications FSB DC Specifications10. BSEL20 and VID50 Signal Group DC Specifications Symbol Parameter Max Unit12. Pwrgood Input and TAP Signal Group DC Specifications 13. GTL+ Asynchronous Signal Group DC SpecificationsSymbol Parameter Min Typ Max Units 14. Vttpwrgd DC Specifications15. Bootselect and MSID10 DC Specifications 16. GTL+ Bus Voltage Definitions17. Core Frequency to FSB Multiplier Configuration Clock SpecificationsFSB Frequency Select Signals FSB Clock BCLK10 and Processor ClockingFSB Frequency Phase Lock Loop PLL and Filter18. BSEL20 Frequency Table for BCLK10 133 MHzPhase Lock Loop PLL Filter Requirements Package Mechanical Specifications Package Mechanical DrawingProcessor Package Drawing Package Mechanical Specifications Package Mechanical Specifications Processor Component Keep-Out Zones Package Loading SpecificationsProcessor Loading Specifications Package Handling GuidelinesProcessor Materials Package Insertion SpecificationsProcessor Mass Specification Processor MarkingsProcessor Top-Side Marking Example Intel Pentium D Processor Processor Land Coordinates Processor Land Coordinates, Top ViewLand Listing and Signal Descriptions Processor Land AssignmentsLandout Diagram Top View Left Side Landout Diagram Top View Right Side Land Name Signal Buffer Direction Type Alphabetical Land AssignmentsDBI0# GTLREF1 VCC AC8 VCC AK8 Vccmb AN5 VSS AA3 VSS AJ4 E11 Power/Other Vssmb AN6 Land Land Name Signal Buffer Direction Type Numerical Land AssignmentReserved ADS# Reserved DEFER# J12 N30 AA1 Vttoutright AD4 VSS AH1 VSS AK2 VSS AN1 VSS Request Signals Alphabetical Signals ReferenceSignal Description Sheet 1 Name Type DescriptionSignal Description Sheet 2 NameBus Signal Data Bus Signals Signal Description Sheet 3Data Group Signal Description Sheet 4 Signal Description Sheet 5 RESET# Signal Description Sheet 6Pwrgood Signal Description Sheet 7 Signal Description Sheet 8 Land Listing and Signal Descriptions Processor Thermal Specifications Thermal Specifications and Design ConsiderationsThermal Specifications Minimum Maximum T C C Processor Thermal SpecificationsGHz Power Maximum T C Thermal Profile for the Pentium D Processor with PRB=1Power Thermal Profile for the Pentium D Processor with PRB=0Thermal Metrology Processor Thermal FeaturesThermal Monitor On-Demand Mode PROCHOT# SignalFORCEPR# Signal Pin Thermal Diode THERMTRIP# SignalTcontrol and Fan Speed Reduction Thermal Diode ParametersThermal Diode Interface Signal Name Land Number Signal DescriptionDiode anode Thermal Specifications and Design Considerations Clock Control and Low Power States FeaturesPower-On Configuration Options Power-On Configuration Option SignalsHalt and Enhanced Halt Powerdown States Normal StateEnhanced Halt Powerdown State Stop-Grant StateEnhanced Halt Snoop or Halt Snoop State, Grant Snoop State Enhanced Intel SpeedStep TechnologyBoxed Processor Specifications Mechanical Representation of the Boxed ProcessorMechanical Specifications Boxed Processor Cooling Solution DimensionsFan Heatsink Power Supply Boxed Processor Fan Heatsink WeightElectrical Requirements Description Min Typ Max Unit Fan Heatsink Power and Signal Specifications+12 V 12 volt fan power supply Sense frequencyThermal Specifications Boxed Processor Cooling RequirementsBoxed Processor Specifications Boxed Processor Fan Boxed Processor Fan Speed Variable Speed FanFan operates at its highest speed Boxed Processor Specifications Mechanical Representation of the Boxed Processor Cooling Solution Dimensions Assembly Stack Including the Support and Retention Module Boxed Processor Support and Retention Module SRMSense Sense frequency ControlDatasheet 101 Boxed Processor TMA Set Points Boxed Processor Boxed Processor Fan SpeedDatasheet 103 104 Mechanical Considerations Debug Tools SpecificationsLogic Analyzer Interface LAI Electrical Considerations106

830 specifications

The Intel 830 chipset, introduced in the early 2000s, marked a significant evolution in Intel's chipset architecture for desktop and mobile computing. Known for its support of the Pentium 4 processors, the 830 chipset was tailored for both performance and stability, making it an appealing choice for OEMs and enthusiasts alike.

One of the standout features of the Intel 830 chipset is its support for DDR SDRAM, providing a much-needed boost in memory bandwidth compared to its predecessors. With dual-channel memory support, the chipset could utilize two memory modules simultaneously, which effectively doubled the data transfer rate and enhanced overall system performance. This made the Intel 830 particularly beneficial for applications requiring high memory throughput, such as multimedia processing and gaming.

Another important characteristic of the Intel 830 was its integrated graphics support, featuring Intel's Extreme Graphics technology. This integration allowed for decent graphics performance without the need for a dedicated GPU, making it suitable for budget systems and everyday computing tasks. However, for power users and gaming enthusiasts, the option to incorporate a discrete graphics card remained available through the provided PCI Express x16 slot.

The Intel 830 chipset also boasted advanced I/O capabilities, including support for USB 2.0, which provided faster data transfer rates compared to USB 1.1, and enhanced IDE interfaces for connecting hard drives and optical devices. With its Hyper-Threading technology support, the chipset allowed for improved multitasking efficiency, enabling a single processor to execute multiple threads simultaneously, a feature that was particularly beneficial in server environments and complex computing tasks.

In terms of connectivity, the Intel 830 supported multiple bus interfaces, including PCI Express and AGP, thereby enabling users to expand their systems with various add-on cards. This flexibility contributed to the chipset's longevity in the marketplace, as it catered to a wide range of user needs from light computing to intensive gaming and content creation.

In summary, the Intel 830 chipset combined enhanced memory capabilities, integrated graphics performance, robust I/O features, and flexible expansion options, making it a versatile choice for various computing environments during its time. It played a key role in shaping the landscape of early 2000s computing, paving the way for future advancements in chipset technology. Its legacy continues to influence modern computing architectures, illustrating the lasting impact of Intel’s innovative design principles.