Intel 830 manual Reserved DEFER#

Page 58

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

Land Name

Signal Buffer

Direction

#

Type

 

 

 

 

 

 

F19

VSS

Power/Other

 

 

 

 

 

F20

D41#

Source Synch

Input/Output

 

 

 

 

F21

D43#

Source Synch

Input/Output

 

 

 

 

F22

VSS

Power/Other

 

 

 

 

 

F23

RESERVED

 

 

 

 

 

 

F24

TESTHI7

Power/Other

Input

 

 

 

 

F25

TESTHI2

Power/Other

Input

 

 

 

 

F26

TESTHI0

Power/Other

Input

 

 

 

 

F27

VTT_SEL

Power/Other

Output

 

 

 

 

F28

BCLK0

Clock

Input

 

 

 

 

F29

RESERVED

 

 

 

 

 

 

G1

VSS

Power/Other

 

 

 

 

 

G2

COMP2

Power/Other

Input

 

 

 

 

G3

TESTHI8

Power/Other

Input

 

 

 

 

G4

TESTHI9

Power/Other

Input

 

 

 

 

G5

FC7

Source Synch

Output

 

 

 

 

G6

RESERVED

 

 

 

 

 

 

G7

DEFER#

Common Clock

Input

 

 

 

 

G8

BPRI#

Common Clock

Input

 

 

 

 

G9

D16#

Source Synch

Input/Output

 

 

 

 

G10

RESERVED

 

 

 

 

 

 

G11

DBI1#

Source Synch

Input/Output

 

 

 

 

G12

DSTBN1#

Source Synch

Input/Output

 

 

 

 

G13

D27#

Source Synch

Input/Output

 

 

 

 

G14

D29#

Source Synch

Input/Output

 

 

 

 

G15

D31#

Source Synch

Input/Output

 

 

 

 

G16

D32#

Source Synch

Input/Output

 

 

 

 

G17

D36#

Source Synch

Input/Output

 

 

 

 

G18

D35#

Source Synch

Input/Output

 

 

 

 

G19

DSTBP2#

Source Synch

Input/Output

 

 

 

 

G20

DSTBN2#

Source Synch

Input/Output

 

 

 

 

G21

D44#

Source Synch

Input/Output

 

 

 

 

G22

D47#

Source Synch

Input/Output

 

 

 

 

G23

RESET#

Common Clock

Input

 

 

 

 

G24

TESTHI6

Power/Other

Input

 

 

 

 

G25

TESTHI3

Power/Other

Input

 

 

 

 

G26

TESTHI5

Power/Other

Input

 

 

 

 

G27

TESTHI4

Power/Other

Input

 

 

 

 

G28

BCLK1

Clock

Input

 

 

 

 

G29

BSEL0

Power/Other

Output

 

 

 

 

G30

BSEL2

Power/Other

Output

 

 

 

 

Table 4-2. Numerical Land Assignment

Land

Land Name

Signal Buffer

Direction

#

Type

 

 

 

 

 

 

H1

GTLREF0

Power/Other

Input

 

 

 

 

H2

GTLREF1

Power/Other

Input

 

 

 

 

H3

VSS

Power/Other

 

 

 

 

 

H4

RSP#

Common Clock

Input

 

 

 

 

H5

TESTHI10

Power/Other

Input

 

 

 

 

H6

VSS

Power/Other

 

 

 

 

 

H7

VSS

Power/Other

 

 

 

 

 

H8

VSS

Power/Other

 

 

 

 

 

H9

VSS

Power/Other

 

 

 

 

 

H10

VSS

Power/Other

 

 

 

 

 

H11

VSS

Power/Other

 

 

 

 

 

H12

VSS

Power/Other

 

 

 

 

 

H13

VSS

Power/Other

 

 

 

 

 

H14

VSS

Power/Other

 

 

 

 

 

H15

DP1#

Common Clock

Input/Output

 

 

 

 

H16

DP2#

Common Clock

Input/Output

 

 

 

 

H17

VSS

Power/Other

 

 

 

 

 

H18

VSS

Power/Other

 

 

 

 

 

H19

VSS

Power/Other

 

 

 

 

 

H20

VSS

Power/Other

 

 

 

 

 

H21

VSS

Power/Other

 

 

 

 

 

H22

VSS

Power/Other

 

 

 

 

 

H23

VSS

Power/Other

 

 

 

 

 

H24

VSS

Power/Other

 

 

 

 

 

H25

VSS

Power/Other

 

 

 

 

 

H26

VSS

Power/Other

 

 

 

 

 

H27

VSS

Power/Other

 

 

 

 

 

H28

VSS

Power/Other

 

 

 

 

 

H29

GTLREF_SEL

Power/Other

Output

 

 

 

 

H30

BSEL1

Power/Other

Output

 

 

 

 

J1

VTT_OUT_LEFT

Power/Other

Output

 

 

 

 

J2

FC3

Power/Other

Input

 

 

 

 

J3

FC22

Power/Other

Input

 

 

 

 

J4

VSS

Power/Other

 

 

 

 

 

J5

REQ1#

Source Synch

Input/Output

 

 

 

 

J6

REQ4#

Source Synch

Input/Output

 

 

 

 

J7

VSS

Power/Other

 

 

 

 

 

J8

VCC

Power/Other

 

 

 

 

 

J9

VCC

Power/Other

 

 

 

 

 

J10

VCC

Power/Other

 

 

 

 

 

J11

VCC

Power/Other

 

 

 

 

 

58

Datasheet

Image 58
Contents Datasheet Intel Pentium D Processor 800Δ SequenceContents Contents Halt and Enhanced Halt Powerdown States Figures Tables Revision Description Date Revision HistoryInitial release May Contents Intel Pentium D Processor 800 Sequence Features Contents Introduction Terminology Processor Packaging TerminologyReferences ReferencesIntroduction Decoupling Guidelines Electrical SpecificationsPower and Ground Lands VCC DecouplingVoltage Identification FSB DecouplingVoltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0Reserved, Unused, FC and Testhi Signals Symbol Parameter Min Max Unit Voltage and Current SpecificationsDC Voltage and Current Specifications Absolute Maximum and Minimum RatingsVID Voltage and Current SpecificationsSymbol Parameter Min Typ Max Unit Vttout ICC065 Icc a Voltage Deviation from VID Setting V 1, 2000 072Icc a 013 033 000 019007 026 020 040Icc a Magnitude of V CC overshoot above VID 050 VCC Overshoot SpecificationVCC Overshoot Specifications Time duration of V CC overshoot above VIDFSB Signal Groups Signaling SpecificationsDie Voltage Validation Signals FSB Signal GroupsSignal Group Signals Associated StrobeSignal Characteristics 2 GTL+ Asynchronous SignalsSignal Reference Voltages 11. GTL+ Signal Group DC Specifications FSB DC Specifications10. BSEL20 and VID50 Signal Group DC Specifications Symbol Parameter Max Unit12. Pwrgood Input and TAP Signal Group DC Specifications 13. GTL+ Asynchronous Signal Group DC SpecificationsSymbol Parameter Min Typ Max Units 14. Vttpwrgd DC Specifications15. Bootselect and MSID10 DC Specifications 16. GTL+ Bus Voltage Definitions17. Core Frequency to FSB Multiplier Configuration Clock SpecificationsFSB Frequency Select Signals FSB Clock BCLK10 and Processor ClockingFSB Frequency Phase Lock Loop PLL and Filter18. BSEL20 Frequency Table for BCLK10 133 MHzPhase Lock Loop PLL Filter Requirements Package Mechanical Specifications Package Mechanical DrawingProcessor Package Drawing Package Mechanical Specifications Package Mechanical Specifications Processor Component Keep-Out Zones Package Loading SpecificationsProcessor Loading Specifications Package Handling GuidelinesProcessor Materials Package Insertion SpecificationsProcessor Mass Specification Processor MarkingsProcessor Top-Side Marking Example Intel Pentium D Processor Processor Land Coordinates Processor Land Coordinates, Top ViewLand Listing and Signal Descriptions Processor Land AssignmentsLandout Diagram Top View Left Side Landout Diagram Top View Right Side Land Name Signal Buffer Direction Type Alphabetical Land AssignmentsDBI0# GTLREF1 VCC AC8 VCC AK8 Vccmb AN5 VSS AA3 VSS AJ4 E11 Power/Other Vssmb AN6 Land Land Name Signal Buffer Direction Type Numerical Land AssignmentReserved ADS# Reserved DEFER# J12 N30 AA1 Vttoutright AD4 VSS AH1 VSS AK2 VSS AN1 VSS Request Signals Alphabetical Signals ReferenceSignal Description Sheet 1 Name Type DescriptionSignal Description Sheet 2 NameBus Signal Data Bus Signals Signal Description Sheet 3Data Group Signal Description Sheet 4 Signal Description Sheet 5 RESET# Signal Description Sheet 6Pwrgood Signal Description Sheet 7 Signal Description Sheet 8 Land Listing and Signal Descriptions Processor Thermal Specifications Thermal Specifications and Design ConsiderationsThermal Specifications Minimum Maximum T C C Processor Thermal SpecificationsGHz Power Maximum T C Thermal Profile for the Pentium D Processor with PRB=1Power Thermal Profile for the Pentium D Processor with PRB=0Thermal Metrology Processor Thermal FeaturesThermal Monitor On-Demand Mode PROCHOT# SignalFORCEPR# Signal Pin Thermal Diode THERMTRIP# SignalTcontrol and Fan Speed Reduction Thermal Diode ParametersThermal Diode Interface Signal Name Land Number Signal DescriptionDiode anode Thermal Specifications and Design Considerations Clock Control and Low Power States FeaturesPower-On Configuration Options Power-On Configuration Option SignalsHalt and Enhanced Halt Powerdown States Normal StateEnhanced Halt Powerdown State Stop-Grant StateEnhanced Halt Snoop or Halt Snoop State, Grant Snoop State Enhanced Intel SpeedStep TechnologyBoxed Processor Specifications Mechanical Representation of the Boxed ProcessorMechanical Specifications Boxed Processor Cooling Solution DimensionsFan Heatsink Power Supply Boxed Processor Fan Heatsink WeightElectrical Requirements Description Min Typ Max Unit Fan Heatsink Power and Signal Specifications+12 V 12 volt fan power supply Sense frequencyThermal Specifications Boxed Processor Cooling RequirementsBoxed Processor Specifications Boxed Processor Fan Boxed Processor Fan Speed Variable Speed FanFan operates at its highest speed Boxed Processor Specifications Mechanical Representation of the Boxed Processor Cooling Solution Dimensions Assembly Stack Including the Support and Retention Module Boxed Processor Support and Retention Module SRMSense Sense frequency ControlDatasheet 101 Boxed Processor TMA Set Points Boxed Processor Boxed Processor Fan SpeedDatasheet 103 104 Mechanical Considerations Debug Tools SpecificationsLogic Analyzer Interface LAI Electrical Considerations106

830 specifications

The Intel 830 chipset, introduced in the early 2000s, marked a significant evolution in Intel's chipset architecture for desktop and mobile computing. Known for its support of the Pentium 4 processors, the 830 chipset was tailored for both performance and stability, making it an appealing choice for OEMs and enthusiasts alike.

One of the standout features of the Intel 830 chipset is its support for DDR SDRAM, providing a much-needed boost in memory bandwidth compared to its predecessors. With dual-channel memory support, the chipset could utilize two memory modules simultaneously, which effectively doubled the data transfer rate and enhanced overall system performance. This made the Intel 830 particularly beneficial for applications requiring high memory throughput, such as multimedia processing and gaming.

Another important characteristic of the Intel 830 was its integrated graphics support, featuring Intel's Extreme Graphics technology. This integration allowed for decent graphics performance without the need for a dedicated GPU, making it suitable for budget systems and everyday computing tasks. However, for power users and gaming enthusiasts, the option to incorporate a discrete graphics card remained available through the provided PCI Express x16 slot.

The Intel 830 chipset also boasted advanced I/O capabilities, including support for USB 2.0, which provided faster data transfer rates compared to USB 1.1, and enhanced IDE interfaces for connecting hard drives and optical devices. With its Hyper-Threading technology support, the chipset allowed for improved multitasking efficiency, enabling a single processor to execute multiple threads simultaneously, a feature that was particularly beneficial in server environments and complex computing tasks.

In terms of connectivity, the Intel 830 supported multiple bus interfaces, including PCI Express and AGP, thereby enabling users to expand their systems with various add-on cards. This flexibility contributed to the chipset's longevity in the marketplace, as it catered to a wide range of user needs from light computing to intensive gaming and content creation.

In summary, the Intel 830 chipset combined enhanced memory capabilities, integrated graphics performance, robust I/O features, and flexible expansion options, making it a versatile choice for various computing environments during its time. It played a key role in shaping the landscape of early 2000s computing, paving the way for future advancements in chipset technology. Its legacy continues to influence modern computing architectures, illustrating the lasting impact of Intel’s innovative design principles.