Intel 830 manual Phase Lock Loop PLL and Filter, BSEL20 Frequency Table for BCLK10, FSB Frequency

Electrical Specifications

Table 2-18. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2	BSEL1	BSEL0	FSB Frequency
L	L	L	RESERVED
L	L	H	133 MHz
L	H	H	RESERVED
L	H	L	200 MHz
H	L	L	RESERVED
H	L	H	RESERVED
H	H	H	RESERVED
H	H	L	RESERVED

2.7.3Phase Lock Loop (PLL) and Filter

VCCA and VCCIOPLL are power sources required by the PLL clock generators for the Pentium D processor. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VTT.

The AC low-pass requirements, with input at VTT are as follows:

•< 0.2 dB gain in pass band

•< 0.5 dB attenuation in pass band < 1 Hz

•> 34 dB attenuation from 1 MHz to 66 MHz

•> 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 2-4.

Datasheet 33