Intel 830 manual Signal Description Sheet 6, Pwrgood, Reset#

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Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 6 of 8)

 

 

 

 

 

Name

Type

Description

 

 

 

 

 

 

 

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error

 

 

 

without a bus protocol violation. It may be driven by all processor FSB agents.

 

 

 

MCERR# assertion conditions are configurable at a system level. Assertion

 

 

 

options are defined by the following options:

 

 

Input/

• Enabled or disabled.

 

MCERR#

• Asserted, if configured, for internal errors along with IERR#.

 

Output

 

 

• Asserted, if configured, by the request initiator of a bus transaction after it

 

 

 

 

 

 

observes an error.

 

 

 

• Asserted by any bus agent when it observes an error in a bus transaction.

 

 

 

For more details regarding machine check architecture, refer to the IA-32

 

 

 

Software Developer’s Manual, Volume 3: System Programming Guide.

 

 

 

 

 

 

 

MSID0 is used to indicate to the processor whether the platform supports

 

 

 

processors with the Platform Requirement Bit (PRB) set. A processor with

 

MSID[1:0]

Input

PRB = 1 will only boot if its MSID0 pin is electrically low. A processor with

 

 

 

PRB = 0 will ignore this input.

 

 

 

MSID1 is ignored by the processor.

 

 

 

 

 

 

 

For the Pentium D processor PROCHOT# can be configured via BIOS as an

 

 

Output

output or a bi-directional signal.

 

 

As an output, PROCHOT# (Processor Hot) will go active when the processor

 

 

or

temperature monitoring sensor detects that one or both cores has reached its

 

PROCHOT#

Input/

maximum safe operating temperature. This indicates that the processor

 

 

Output

Thermal Control Circuit (TCC) has been activated, if enabled.

 

 

 

As a bi-directional signal, assertion of PROCHOT# by the system will activate

 

 

 

the TCC, if enabled, for both cores. The TCC will remain active until the system

 

 

 

de-asserts PROCHOT#. See Section 5.2.3 for more details.

 

 

 

 

 

 

 

PWRGOOD (Power Good) is a processor input. The processor requires this

 

 

 

signal to be a clean indication that the clocks and power supplies are stable and

 

 

 

within their specifications. ‘Clean’ implies that the signal will remain low

 

 

 

(capable of sinking leakage current), without glitches, from the time that the

 

 

 

power supplies are turned on until they come within specification. The signal

 

PWRGOOD

Input

must then transition monotonically to a high state. PWRGOOD can be driven

 

 

 

inactive at any time, but clocks and power must again be stable before a

 

 

 

subsequent rising edge of PWRGOOD.

 

 

 

The PWRGOOD signal must be supplied to the processor; it is used to protect

 

 

 

internal circuits against voltage sequencing issues. It should be driven high

 

 

 

throughout boundary scan operation.

 

 

 

 

 

 

 

REQ[4:0]# (Request Command) must connect the appropriate pins/lands of all

 

 

Input/

processor FSB agents. They are asserted by the current bus owner to define

 

REQ[4:0]#

the currently active transaction type. These signals are source synchronous to

 

Output

 

 

ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity

 

 

 

 

 

 

checking of these signals.

 

 

 

 

 

 

 

Asserting the RESET# signal resets the processor to a known state and

 

 

 

invalidates its internal caches without writing back any of their contents. For a

 

 

 

power-on Reset, RESET# must stay active for at least one millisecond after

 

 

 

VCC and BCLK have reached their proper specifications. On observing active

 

 

 

RESET#, all FSB agents will de-assert their outputs within two clocks. RESET#

 

RESET#

Input

must not be kept asserted for more than 10 ms while PWRGOOD is asserted.

 

A number of bus signals are sampled at the active-to-inactive transition of

 

 

 

 

 

 

RESET# for power-on configuration. These configuration options are described

 

 

 

in the Section 6.1.

 

 

 

This signal does not have on-die termination and must be terminated on the

 

 

 

system board.

 

 

 

 

 

 

 

RS[2:0]# (Response Status) are driven by the response agent (the agent

 

RS[2:0]#

Input

responsible for completion of the current transaction), and must connect the

 

 

 

appropriate pins/lands of all processor FSB agents.

 

 

 

 

Datasheet

71

Image 71
Contents Intel Pentium D Processor 800Δ Sequence DatasheetContents Contents Halt and Enhanced Halt Powerdown States Figures Tables Initial release May Revision HistoryRevision Description Date Contents Intel Pentium D Processor 800 Sequence Features Contents Introduction Processor Packaging Terminology TerminologyReferences ReferencesIntroduction VCC Decoupling Electrical SpecificationsPower and Ground Lands Decoupling GuidelinesFSB Decoupling Voltage IdentificationVID5 VID4 VID3 VID2 VID1 VID0 Voltage Identification DefinitionReserved, Unused, FC and Testhi Signals Absolute Maximum and Minimum Ratings Voltage and Current SpecificationsDC Voltage and Current Specifications Symbol Parameter Min Max UnitVttout ICC Voltage and Current SpecificationsSymbol Parameter Min Typ Max Unit VID072 Icc a Voltage Deviation from VID Setting V 1, 2000 065Icc a 020 040 000 019007 026 013 033Icc a Time duration of V CC overshoot above VID VCC Overshoot SpecificationVCC Overshoot Specifications Magnitude of V CC overshoot above VID 050Die Voltage Validation Signaling SpecificationsFSB Signal Groups Signals Associated Strobe FSB Signal GroupsSignal Group SignalsSignal Reference Voltages 2 GTL+ Asynchronous SignalsSignal Characteristics Symbol Parameter Max Unit FSB DC Specifications10. BSEL20 and VID50 Signal Group DC Specifications 11. GTL+ Signal Group DC Specifications13. GTL+ Asynchronous Signal Group DC Specifications 12. Pwrgood Input and TAP Signal Group DC Specifications16. GTL+ Bus Voltage Definitions 14. Vttpwrgd DC Specifications15. Bootselect and MSID10 DC Specifications Symbol Parameter Min Typ Max UnitsFSB Clock BCLK10 and Processor Clocking Clock SpecificationsFSB Frequency Select Signals 17. Core Frequency to FSB Multiplier Configuration133 MHz Phase Lock Loop PLL and Filter18. BSEL20 Frequency Table for BCLK10 FSB FrequencyPhase Lock Loop PLL Filter Requirements Package Mechanical Drawing Package Mechanical SpecificationsProcessor Package Drawing Package Mechanical Specifications Package Mechanical Specifications Package Handling Guidelines Package Loading SpecificationsProcessor Loading Specifications Processor Component Keep-Out ZonesProcessor Markings Package Insertion SpecificationsProcessor Mass Specification Processor MaterialsProcessor Top-Side Marking Example Intel Pentium D Processor Processor Land Coordinates, Top View Processor Land CoordinatesProcessor Land Assignments Land Listing and Signal DescriptionsLandout Diagram Top View Left Side Landout Diagram Top View Right Side Alphabetical Land Assignments Land Name Signal Buffer Direction TypeDBI0# GTLREF1 VCC AC8 VCC AK8 Vccmb AN5 VSS AA3 VSS AJ4 E11 Power/Other Vssmb AN6 Numerical Land Assignment Land Land Name Signal Buffer Direction TypeReserved ADS# Reserved DEFER# J12 N30 AA1 Vttoutright AD4 VSS AH1 VSS AK2 VSS AN1 VSS Name Type Description Alphabetical Signals ReferenceSignal Description Sheet 1 Request SignalsName Signal Description Sheet 2Data Group Signal Description Sheet 3Bus Signal Data Bus Signals Signal Description Sheet 4 Signal Description Sheet 5 Pwrgood Signal Description Sheet 6RESET# Signal Description Sheet 7 Signal Description Sheet 8 Land Listing and Signal Descriptions Thermal Specifications Thermal Specifications and Design ConsiderationsProcessor Thermal Specifications GHz Processor Thermal SpecificationsMinimum Maximum T C C Thermal Profile for the Pentium D Processor with PRB=1 Power Maximum T CThermal Profile for the Pentium D Processor with PRB=0 PowerThermal Monitor Processor Thermal FeaturesThermal Metrology PROCHOT# Signal On-Demand ModeFORCEPR# Signal Pin Thermal Diode Parameters THERMTRIP# SignalTcontrol and Fan Speed Reduction Thermal DiodeDiode anode Signal Name Land Number Signal DescriptionThermal Diode Interface Thermal Specifications and Design Considerations Power-On Configuration Option Signals FeaturesPower-On Configuration Options Clock Control and Low Power StatesNormal State Halt and Enhanced Halt Powerdown StatesStop-Grant State Enhanced Halt Powerdown StateEnhanced Intel SpeedStep Technology Enhanced Halt Snoop or Halt Snoop State, Grant Snoop StateMechanical Representation of the Boxed Processor Boxed Processor SpecificationsBoxed Processor Cooling Solution Dimensions Mechanical SpecificationsElectrical Requirements Boxed Processor Fan Heatsink WeightFan Heatsink Power Supply Sense frequency Fan Heatsink Power and Signal Specifications+12 V 12 volt fan power supply Description Min Typ Max UnitBoxed Processor Cooling Requirements Thermal SpecificationsBoxed Processor Specifications Fan operates at its highest speed Variable Speed FanBoxed Processor Fan Boxed Processor Fan Speed Boxed Processor Specifications Mechanical Representation of the Boxed Processor Cooling Solution Dimensions Boxed Processor Support and Retention Module SRM Assembly Stack Including the Support and Retention ModuleControl Sense Sense frequencyDatasheet 101 Boxed Processor Boxed Processor Fan Speed Boxed Processor TMA Set PointsDatasheet 103 104 Electrical Considerations Debug Tools SpecificationsLogic Analyzer Interface LAI Mechanical Considerations106

830 specifications

The Intel 830 chipset, introduced in the early 2000s, marked a significant evolution in Intel's chipset architecture for desktop and mobile computing. Known for its support of the Pentium 4 processors, the 830 chipset was tailored for both performance and stability, making it an appealing choice for OEMs and enthusiasts alike.

One of the standout features of the Intel 830 chipset is its support for DDR SDRAM, providing a much-needed boost in memory bandwidth compared to its predecessors. With dual-channel memory support, the chipset could utilize two memory modules simultaneously, which effectively doubled the data transfer rate and enhanced overall system performance. This made the Intel 830 particularly beneficial for applications requiring high memory throughput, such as multimedia processing and gaming.

Another important characteristic of the Intel 830 was its integrated graphics support, featuring Intel's Extreme Graphics technology. This integration allowed for decent graphics performance without the need for a dedicated GPU, making it suitable for budget systems and everyday computing tasks. However, for power users and gaming enthusiasts, the option to incorporate a discrete graphics card remained available through the provided PCI Express x16 slot.

The Intel 830 chipset also boasted advanced I/O capabilities, including support for USB 2.0, which provided faster data transfer rates compared to USB 1.1, and enhanced IDE interfaces for connecting hard drives and optical devices. With its Hyper-Threading technology support, the chipset allowed for improved multitasking efficiency, enabling a single processor to execute multiple threads simultaneously, a feature that was particularly beneficial in server environments and complex computing tasks.

In terms of connectivity, the Intel 830 supported multiple bus interfaces, including PCI Express and AGP, thereby enabling users to expand their systems with various add-on cards. This flexibility contributed to the chipset's longevity in the marketplace, as it catered to a wide range of user needs from light computing to intensive gaming and content creation.

In summary, the Intel 830 chipset combined enhanced memory capabilities, integrated graphics performance, robust I/O features, and flexible expansion options, making it a versatile choice for various computing environments during its time. It played a key role in shaping the landscape of early 2000s computing, paving the way for future advancements in chipset technology. Its legacy continues to influence modern computing architectures, illustrating the lasting impact of Intel’s innovative design principles.