Texas Instruments SPRU938B manual Initialization, Auto-Negotiation

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Peripheral Architecture

Note: Not servicing read operations results in deadlock. The only way to recover from a deadlock situation is to perform a hard reset. Read operations are typically not serviced due to read requests that are issued to a non-existent remote VLYNQ device or they are not serviced due to trying to perform reads on the VLYNQ memory map prior to establishing the link.

Generally, you should not use read operations to transfer data packets since the serial nature of the interface could potentially result in longer latencies. See Appendix B for more information.

2.6Initialization

Since VLYNQ devices can be controlled solely over the serial interface (that is, no local CPU exists), an automatic reliable initialization sequence (without user configuration) establishes a connection between two VLYNQ devices, just after a VLYNQ module is enabled and auto-negotiation occurs. Auto-negotiation is defined in Section 2.7. The same sequence is used to recover from error conditions. However, it is important to ensure that the appropriate bits are configured in the pin mux registers to ensure that the VLYNQ peripheral is active.

Bit 0 in the VLYNQ status register (LINK bit) is set to 1 when a link is established.

A link pulse timer generates a periodic link code every 2048 serial clock cycles. The link is lost when time expires and no link code has been detected during a period of 4096 serial clock cycles.

2.7Auto-Negotiation

Auto-negotiation occurs after reset. It involves placing a negotiation protocol in the outbound data and processing the inbound data to establish connection information. The width of the data pins on the serial interface is automatically determined at reset as a part of the initialization sequence. For a connection between two VLYNQ devices of version 2.0 and later (VLYNQ on DM643x device is version 2.6), the negotiation protocol using the available serial pins is used to convey the maximum width capability of each device. The TXD data pins are not required to have the same width as the RXD data pins.

The auto width negotiation does not occur until after completion of the VLYNQ 1.x legacy width configuration, which involves a period of 2000 VLYNQ 1.x system clock cycles for connection to VLYNQ 1.x devices. After the VLYNQ 1.x has determined its width, it receives the VLYNQ2.x auto width negotiation protocol. The VLYNQ 1.x device does not recognize this protocol and transmits error codes over the serial interface. The received error codes allow the VLYNQ 2.x devices to determine how many serial pins are valid on the connected VLYNQ 1.x device.

Once the width is established, VLYNQ further identifies the version (version 1.x or version 2.x ) of the remote VLYNQ. This better determines the capabilities of the connected VLYNQ device. This is software readable via the VLYNQ auto-negotiation register (AUTNGO), bit 16 (0 = Ver 1.x , 1 = Ver 2.x), after the link has been established.

SPRU938B –September 2007

VLYNQ Port

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramProtocol Description Signal DescriptionsVlynq Signal Descriptions Pin MultiplexingVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlInterrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramSerial Bus Error Interrupts Edma Event SupportRemote Interrupts Power Management Endianness ConsiderationsEmulation Considerations Acronym Register Description Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address SizeBit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj RevminControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInstat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr NointpendIntset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field DescriptionsTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field DescriptionsVlynq Port Remote Controller Registers Table A-1. Special 8b/10b Code Groups IntroductionSpecial 8b/10b Code Groups Supported Ordered SetsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZLatency μsec Read PerformanceTable B-3. Relative Performance with Various Latencies ThroughputReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryProducts Applications DSPRfid
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