Texas Instruments SPRU938B manual Vlynq 2.0 Packet Format

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VLYNQ 2.0 Packet Format

A.3.1

Idle (/I/)

The idle ordered sets are transmitted continuously and repetitively whenever the serial interface is idle. Idle is also used in the place of the flowed code in VLYNQ versions 2.0 and later.

A.3.2 End of Packet (/T/)

An end of packet delimiter delineates the ending boundary of a packet.

A.3.3 Byte Disable (/M/)

The byte disable symbol masks bytes for write operations.

A.3.4 Flow Control Enable (/P/)

A flow control enable request is transmitted when a VLYNQ module’s receive FIFO is full or nearly full. This code causes the remote VLYNQ device to cease transmission of data.

A.3.5 Flow Control Disable (/C/)

The flow control disable request is transmitted by a VLYNQ module when RX FIFO resources are available to accommodate additional data.

A.3.6 Error Indication (/E/)

The error indication is transmitted when errors are detected within a packet. Examples of such errors include illegal packet types and code groups.

A.3.7

Init0 (/0/)

The Init0 code group is used during the link initialization sequence. VLYNQ 2.0 and later versions use this code with an extra byte for identifying version 1.X devices.

A.3.8

Init1 (/1/)

The Init1code group is used during the Link initialization sequence. VLYNQ 2.0 and later uses this code with an extra byte for identifying version 1.X devices.

A.3.9

Link (/L/)

The link code group is used during the link initialization sequence. A link code group is also transmitted each time the internal link timer expires.

A.4 VLYNQ 2.0 Packet Format

The VLYNQ 2.0 packet format is shown in Figure A-1and described in Table A-3, where 0 < N < 65. Multi-byte fields are transferred least-significant byte first.

10￿bits

Figure A-1. Packet Format (10-bit Symbol Representation)

10￿bits

10￿bits

<4*10￿bits

N*10￿bits

10￿bits

cmd￿1

cmd￿2

bytecnt

address

data

eop

pkttype

adrmask

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VLYNQ Protocol Specifications

SPRU938B –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlSignal Descriptions Vlynq Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleReset Considerations Software Reset ConsiderationsHardware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterEdma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Vlynq Register Address Space Vlynq Port Controller RegistersBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Revision Register Revid Field DescriptionsRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorInterrupt Priority Vector Status/Clear Register Intpri Interrupt Status/Clear Register IntstatclrNointpend InstatInterrupt Pending/Set Register Intpendset Interrupt Pointer Register IntptrInterrupt Pointer Register Intptr Field Descriptions IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Size 1 Register RAMS1 Receive Address Map Offset 1 Register RAMO1RXADRSIZE1 RXADROFFSET1Receive Address Map Size 2 Register RAMS2 Receive Address Map Offset 2 Register RAMO2RXADRSIZE2 RXADROFFSET2Receive Address Map Size 3 Register RAMS3 Receive Address Map Offset 3 Register RAMO3RXADRSIZE3 RXADROFFSET3Receive Address Map Size 4 Register RAMS4 Receive Address Map Offset 4 Register RAMO4RXADRSIZE4 RXADROFFSET4Chip Version Register Chipver Auto Negotiation Register AutngoChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Introduction Special 8b/10b Code GroupsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesThroughput Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsDSP Products ApplicationsRfid
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