Texas Instruments SPRU938B Interrupt Priority Vector Status/Clear Register Intpri, Nointpend

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VLYNQ Port Registers

3.4Interrupt Priority Vector Status/Clear Register (INTPRI)

The interrupt priority vector status/clear register (INTPRI) displays the highest priority vector with a pending interrupt when read. When writing, only bits [4:0] are valid, and the value represents the vector of the interrupt to be cleared. The INTPRI is shown in Figure 12 and described in Table 9.

Figure 12. Interrupt Priority Vector Status/Clear Register (INTPRI)

31

30

 

 

16

NOINTPEND

 

Reserved

 

 

R-1h

 

R-0

 

 

15

 

5

4

0

 

Reserved

 

 

INSTAT

 

R-0

 

 

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 9. Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions

Bit

Field

Value

Description

31

NOINTPEND

 

Interrupt pending status.

 

 

0

Indicates there is a pending interrupt.

 

 

1

Indicates that there are no pending interrupts from the interrupt status/clear register.

30-5

Reserved

0

Reserved. Always read as 0. Writes have no effect.

4-0

INSTAT

0-1Fh

When read, this field displays the vector that is mapped to the highest priority interrupt bit that is

 

 

 

pending from the interrupt status/clear register (INSTATCLR), with bit 0 as the highest priority, and

 

 

 

bit 31 as the lowest. Writing the vector value back to this field clears the interrupt.

3.5Interrupt Status/Clear Register (INTSTATCLR)

The interrupt status/clear register (INTSTATCLR) indicates the unmasked interrupt status. The INTSTATCLR is shown in Figure 13 and described in Table 10.

Figure 13. Interrupt Status/Clear Register (INTSTATCLR)

31

0

INTCLR

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

Table 10. Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions

Bit

Field

Value

Description

31-0

INTCLR

0-FFFF FFFFh

This field indicates the unmasked status of each interrupt. Writing a 1 to any set bit in this field

 

 

 

clears the corresponding interrupt. If there is a bit set in this register and if the INTLOCAL bit in

 

 

 

the control register (CTRL) is also set, the VLYNQ interrupt (VLQINT) is asserted.

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VLYNQ Port

SPRU938B –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlPin Multiplexing Signal DescriptionsVlynq Signal Descriptions Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts Edma Event SupportRemote Interrupts Power Management Endianness ConsiderationsEmulation Considerations Block Name Start Address End Address Size Vlynq Register Address SpaceVlynq Port Controller Registers Acronym Register DescriptionRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Supported Ordered Sets IntroductionSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secThroughput Read PerformanceTable B-3. Relative Performance with Various Latencies Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsProducts Applications DSPRfid
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