Texas Instruments SPRU938B manual Introduction, Write Performance

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Appendix B

Appendix B Write/Read Performance

B.1 Introduction

The following sections discuss the write versus read performance and how the throughput (read or write) should be calculated for a given data width and serial clock frequency.

Note: The data and throughput calculations shown here are sample calculations for most ideal situations. In general, the data rates depend on a variety of other factors, such as efficiency of read/write burst transactions, ability of buffering up read/write data, and how best it can be serially shifted out without stalling additional read/write data burst, remote and local components , both external and internal (device operations, board considerations, etc.).

B.2 Write Performance

The max write rate describes the maximum available data rate of the serial interface for transmission, taking into consideration the 8b/10b encoding overheads. This is calculated as follows:

Max write rate = VLYNQ Serial Clock (MHZ) × No. of Pins × 8b/10b encoding overhead

The 8b/10b encoding overhead essentially accounts for 20% overhead, thus the actual data throughput after subtraction of the encoding overhead gives a factor of 0.8. For example, if the VLYNQ clock is running at 99 MHZ on a 4 pin per direction interface, the raw data is 99 × 4 or 396 Mbps. After the 8B10B encoding is removed, the maximum write rate is 396 × 0.8 = 316.8 Mbps.

The total throughput on the VLYNQ interface includes both transmit and receive directions. Therefore, for the above configuration, a remote device can also be writing to the local device at the same data rates, then the total throughput is the sum of transmit and receive rates, or 633.6 Mbps.

In addition to the 8b/10b encoding, the packet structure for read/write operations also results in additional overheads. The VLYNQ module can transfer single 32-bit words or a burst of up to sixteen 32-bit words.

The packet structure of the writes is shown below, here each character represents a byte.

Write32 - caaaaddddT

WriteBurst - claaaaddddddddddddT

Where

T - EndOfPacket

d - data, dddd represents additional 32-bit words in burst, up to 16 words.

a - address

c - command

l - length

The example above illustrates that single writes require 6 bytes of overhead, while burst writes require

8 bytes of overhead (due to the additional length of the field). From this, a scaling factor can be calculated (data bytes/total bytes), as show in Table B-1. The actual throughput is then calculated as the [scaling factor] × [max write rate].

Table B-2compares the throughput using a VLYNQ interface running at 76.5 MHZ and 99 MHZ.

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Write/Read Performance

SPRU938B –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlSignal Descriptions Vlynq Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleReset Considerations Software Reset ConsiderationsHardware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterRemote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Vlynq Register Address Space Vlynq Port Controller RegistersBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Revision Register Revid Field DescriptionsRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorInterrupt Priority Vector Status/Clear Register Intpri Interrupt Status/Clear Register IntstatclrNointpend InstatInterrupt Pending/Set Register Intpendset Interrupt Pointer Register IntptrInterrupt Pointer Register Intptr Field Descriptions IntsetTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions Receive Address Map Size 1 Register RAMS1 Receive Address Map Offset 1 Register RAMO1RXADRSIZE1 RXADROFFSET1Receive Address Map Size 2 Register RAMS2 Receive Address Map Offset 2 Register RAMO2RXADRSIZE2 RXADROFFSET2Receive Address Map Size 3 Register RAMS3 Receive Address Map Offset 3 Register RAMO3RXADRSIZE3 RXADROFFSET3Receive Address Map Size 4 Register RAMS4 Receive Address Map Offset 4 Register RAMO4RXADRSIZE4 RXADROFFSET4Chip Version Register Chipver Auto Negotiation Register AutngoChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Introduction Special 8b/10b Code GroupsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesThroughput Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsRfid Products ApplicationsDSP
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