Texas Instruments SPRU938B manual Chip Version Register Chipver, Auto Negotiation Register Autngo

Page 37

www.ti.com

VLYNQ Port Registers

3.17 Chip Version Register (CHIPVER)

VLYNQ allows inter-connection of many VLYNQ devices. In order for software to control the device functions, there must be a mechanism that allows the software to identify VLYNQ devices. Each device that has a VLYNQ module in it has a unique device ID associated with it, which is software readable via a memory-mapped register within the VLYNQ module called the chip version register (CHIPVER). This is also useful in communicating with remote devices, as the local VLYNQ device register map contains a copy of the remote device'sregisters as well. This allows the software to determine the remote chip ID and, hence, determine the remote memory-map without trying to access random remote addresses to find a device ID register. The CHIPVER is shown in Figure 25 and described in Table 22.

 

Figure 25. Chip Version Register (CHIPVER)

31

16

 

DEVREV

 

R-0

15

0

DEVID

R-2Dh

LEGEND: R = Read only; -n= value after reset

Table 22. Chip Version Register (CHIPVER) Field Descriptions

Bit

Field

Value

Description

31-16

DEVREV

0-FFFFh

Device revision. This field reflects the value of the device revision pins.

15-0

DEVID

0-FFFFh

Device ID.

 

 

2Dh

DM643x device ID.

3.18 Auto Negotiation Register (AUTNGO)

The auto negotiation register (AUTNGO) reflects the ability of the VLYNQ module residing in the device to communicate with the remote VLYNQ device on their respective abilities after reset. The AUTNGO is shown in Figure 26 and described in Table 23.

Figure 26. Auto Negotiation Register (AUTNGO)

31

17

16

Reserved

 

2X

R-0

 

R-0

15

 

0

Reserved

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 23. Auto Negotiation Register (AUTNGO) Field Descriptions

Bit

Field

Value

Description

 

31-17

Reserved

0

Reserved. Always read as 0. Writes have no effect.

 

16

2X

 

Version 2.x mode.

 

 

 

0

Indicates that a link was established with a remote device that has a version 1.x VLYNQ module in it.

 

 

 

1

Indicates that a link was established with a remote device that has a version 2.x VLYNQ module in it.

 

15-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

 

SPRU938B –September 2007

VLYNQ Port

37

Submit Documentation Feedback

 

 

Page 36 Page 38
Image 37
Page 36 Page 38
Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramVlynq Signal Descriptions Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramEdma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Vlynq Port Controller Registers Vlynq Register Address SpaceBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Special 8b/10b Code Groups IntroductionSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceThroughput Latency μsecReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryDSP Products ApplicationsRfid
Top Page Image Contents