Texas Instruments SPRU938B manual Read Operations

Page 14

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Peripheral Architecture

2.5.2Read Operations

Read requests from the slave configuration bus interface are written to the outbound CMD FIFO (similar to the write requests). Data is subsequently read from the FIFO and encapsulated into a read request packet. The packet is encoded and serialized before it is transmitted to the remote device. Next, the remote device deserializes, decodes the receive data, and writes the receive data to the inbound CMD FIFO. After reading the address from the FIFO, a master configuration bus interface read operation initiates in the remote device. When the remote master configuration bus interface receives the read data, the data is written to the return data FIFO before it is encoded and serialized. When the receive data reaches the local VLYNQ module, it is deserialized, decoded, and written to the return data FIFO (local device). Finally, the read data is transferred on the local device’s slave configuration interface.

The data flow between two connected VLYNQ devices with read requests that originate from the DM643x device is shown in Figure 6. The remote VLYNQ device returns the read data. Read data is shown with dotted arrows.

Figure 6. Read Operations

 

 

 

System￿clock

 

VLYNQ￿Clock

 

 

 

 

 

 

 

 

 

Serial

 

Slave

Address

Outbound

Outbound

 

8B/10B

TxData

config￿bus

command

TxSM

Serializer

translation

commands

encoding

 

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

Registers

 

 

 

Local￿VLYNC

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

Serial

 

Master

Address

Inbound

Inbound

 

8B/10B

RxData

config￿bus

command

RxSM

Deserializer

translation

commands

decoding

 

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

System￿clock

 

VLYNQ￿Clock

 

 

 

 

 

 

 

 

 

Serial

 

Slave

Address

Outbound

Outbound

 

8B/10B

TxData

config￿bus

command

TxSM

Serializer

translation

commands

encoding

 

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

Registers

 

 

 

Remote￿VLYNQ

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

Serial

 

Master

Address

Inbound

Inbound

 

8B/10B

RxData

config￿bus

command

RxSM

Deserializer

translation

commands

decoding

 

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

VLYNQ Port

 

 

 

 

SPRU938B –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlPin Multiplexing Signal DescriptionsVlynq Signal Descriptions Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterRemote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Block Name Start Address End Address Size Vlynq Register Address SpaceVlynq Port Controller Registers Acronym Register DescriptionRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Supported Ordered Sets IntroductionSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secThroughput Read PerformanceTable B-3. Relative Performance with Various Latencies Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsRfid Products ApplicationsDSP