Texas Instruments SPRU938B manual Status Register Stat Field Descriptions

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VLYNQ Port Registers

3.3Status Register (STAT)

The status register (STAT) is used to detect conditions that may be of interest to the system designer. The STAT is shown in Figure 11 and described in Table 8.

Figure 11. Status Register (STAT)

31	28	27	24	23	20	19	15
Reserved		SWIDTHIN		SWIDTHOUT		Reserved
	R-0		R-0		R-0		R-0
14			12	11	10	9	8
	RXCURRENTSAMPLE			RTM	IFLOW	OFLOW	RERROR
		R-0		R-1	R-0	R-0	W1C-0
7	6	5	4	3	2	1	0
LERROR	NFEMPTY3	NFEMPTY2	NFEMPTY1	NFEMPTY0	SPEND	MPEND	LINK
W1C-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear bit; -n= value after reset; x= reset value is indeterminate

Table 8. Status Register (STAT) Field Descriptions

Bit	Field	Value	Description
31-28	Reserved	0	Reserved. Always read as 0. Writes have no effect.
27-24	SWIDTHIN	0-Fh	Size of the inbound serial data. Indicates the number of receive pins that are being used to
		0-Fh	establish the serial interface.
			establish the serial interface.
		0	No pins used
		1h	1	RX pin used
		2h	2	RX pins used
		3h	3	RX pins used
		4h	4	RX pins used
		5h-Fh	Reserved
23-20	SWIDTHOUT	0-Fh	Size of the outbound serial data. Indicates the number of transmit pins that are being used
			to establish the serial interface.
		0	No pins used
		1h	1	TX pin used
		2h	2	TX pins used
		3h	3	TX pins used
		4h	4	TX pins used
		5h-Fh	Reserved
19-15	Reserved	0	Reserved. Always read as 0. Writes have no effect.
14-12	RXCURRENTSAMPLE	0-Fh	Current RTM sample. Indicates the current clock sample value used by RTM.
11	RTM	1	RTM enable. Always read as 1. Indicates that the VLYNQ module on the DM643x DMSoC
			has the receive timing manager (RTM).

10 IFLOW

0

1

9 OFLOW

0

1

Inbound flow control.

Free to transmit.

Indicates that a flow control enable request has been received and has stalled transmit until a flow control disable request is received.

Outbound flow control. Indicates the status of the two inbound FIFOs (FIFO1 or FIFO2). Indicates that the internal flow control threshold is not yet reached.

Indicates that the internal flow control threshold has been reached (FIFO1 or FIFO2 is full) and a flow control enable request has been sent to the remote device.

28	VLYNQ Port	SPRU938B –September 2007
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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlSignal Descriptions Vlynq Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleReset Considerations Software Reset ConsiderationsHardware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterEdma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Vlynq Register Address Space Vlynq Port Controller RegistersBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Revision Register Revid Field DescriptionsRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorInterrupt Priority Vector Status/Clear Register Intpri Interrupt Status/Clear Register IntstatclrNointpend InstatInterrupt Pending/Set Register Intpendset Interrupt Pointer Register IntptrInterrupt Pointer Register Intptr Field Descriptions IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Size 1 Register RAMS1 Receive Address Map Offset 1 Register RAMO1RXADRSIZE1 RXADROFFSET1Receive Address Map Size 2 Register RAMS2 Receive Address Map Offset 2 Register RAMO2RXADRSIZE2 RXADROFFSET2Receive Address Map Size 3 Register RAMS3 Receive Address Map Offset 3 Register RAMO3RXADRSIZE3 RXADROFFSET3Receive Address Map Size 4 Register RAMS4 Receive Address Map Offset 4 Register RAMO4RXADRSIZE4 RXADROFFSET4Chip Version Register Chipver Auto Negotiation Register AutngoChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Introduction Special 8b/10b Code GroupsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesThroughput Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsDSP Products ApplicationsRfid