Texas Instruments SPRU938B manual List of Figures

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	List of Figures
1	VLYNQ Port Functional Block Diagram	9
2	External Clock Block Diagram	10
3	Internal Clock Block Diagram	10
4	VLYNQ Module Structure	12
5	Write Operations	13
6	Read Operations	14
7	Example Address Memory Map	17
8	Interrupt Generation Mechanism Block Diagram	21
9	Revision Register (REVID)	25
10	Control Register (CTRL)	26
11	Status Register (STAT)	28
12	Interrupt Priority Vector Status/Clear Register (INTPRI)	30
13	Interrupt Status/Clear Register (INTSTATCLR)	30
14	Interrupt Pending/Set Register (INTPENDSET)	31
15	Interrupt Pointer Register (INTPTR)	31
16	Transmit Address Map Register (XAM)	32
17	Receive Address Map Size 1 Register (RAMS1)	33
18	Receive Address Map Offset 1 Register (RAMO1)	33
19	Receive Address Map Size 2 Register (RAMS2)	34
20	Receive Address Map Offset 2 Register (RAMO2)	34
21	Receive Address Map Size 3 Register (RAMS3)	35
22	Receive Address Map Offset 3 Register (RAMO3)	35
23	Receive Address Map Size 4 Register (RAMS4)	36
24	Receive Address Map Offset 4 Register (RAMO4)	36
25	Chip Version Register (CHIPVER)	37
26	Auto Negotiation Register (AUTNGO)	37
A-1	Packet Format (10-bit Symbol Representation)	40

SPRU938B –September 2007

List of Figures

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramVlynq Signal Descriptions Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramRemote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Vlynq Port Controller Registers Vlynq Register Address SpaceBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Special 8b/10b Code Groups IntroductionSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceThroughput Latency μsecReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryRfid Products ApplicationsDSP