Texas Instruments SPRU938B manual Address Translation

Page 16

www.ti.com

Peripheral Architecture

2.8Address Translation

Remote VLYNQ device(s) are memory mapped to the local (host) device’s address space when a link is established (this is similar to any other on-chip peripherals). Enumerating the VLYNQ devices (single or multiple) into a coherent memory map for accessing each device is part of the initialization sequence.

After the enumeration, the host (local) device can access the remote device address map using local device addresses. The VLYNQ module in the host device manages the address translation of the local address to the remote address. A remote VLYNQ device is mapped to the local device’s address via the address map registers (TX address map, RX address map size n, RX address map offset n, where n = 1 to 4). The transmit side has a contiguous map; the size of the map is the same as the remote device map. Figure 7 illustrates this mapping.

In the local device, the address of the VLYNQ remote memory map in the local configuration space is the transmit address accessing remote devices over the serial interface. The address of the VLYNQ remote memory map is programmed in the TX address map register (XAM). When the local device transmits, first it strips off the transmit address offset in the local device memory map. Then, the local device sends the data with an address offset from the transmit address.

VLYNQ allows each receive packet address to be translated into one of the four mapped regions. The size and offset of each memory region must be aligned to 32-bit words. No restriction is placed on programming the size or on the offset of each mapped region, as long as the total memory that is mapped into these one to four regions is not more then 64 MBytes.

Note: Care should be taken while programming the receive address map size register (RAMSn) and the receive address map offset register (RAMOn) values. These registers should be programmed with valid address locations and memory size to match the device specifications. See the Memory Map Summary and the System Interconnect sections in your device-specific data manual to identify the valid memory regions that can be accessed by an off-chip peer device through the VLYNQ interface.

The transmitted address is used to determine which remote mapped region is being accessed at the remote device. This is achieved by summing each memory size sequentially until the memory size is larger than the transmitted address. The last memory size that is added is the targeted region. A memory size and an offset specify the remote map. The remote map is programmed in the RX address map size register (RAMSn) and in the RX address map offset (RAMOn) in the remote device.

16

VLYNQ Port

SPRU938B –September 2007

Page 15 Page 17
Image 16
Page 15 Page 17
Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlSignal Descriptions Vlynq Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Functional Description Vlynq Module Structure Write Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleReset Considerations Software Reset ConsiderationsHardware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterEdma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Vlynq Register Address Space Vlynq Port Controller RegistersBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Revision Register Revid Field DescriptionsRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorInterrupt Priority Vector Status/Clear Register Intpri Interrupt Status/Clear Register IntstatclrNointpend InstatInterrupt Pending/Set Register Intpendset Interrupt Pointer Register IntptrInterrupt Pointer Register Intptr Field Descriptions IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Size 1 Register RAMS1 Receive Address Map Offset 1 Register RAMO1RXADRSIZE1 RXADROFFSET1Receive Address Map Size 2 Register RAMS2 Receive Address Map Offset 2 Register RAMO2RXADRSIZE2 RXADROFFSET2Receive Address Map Size 3 Register RAMS3 Receive Address Map Offset 3 Register RAMO3RXADRSIZE3 RXADROFFSET3Receive Address Map Size 4 Register RAMS4 Receive Address Map Offset 4 Register RAMO4RXADRSIZE4 RXADROFFSET4Chip Version Register Chipver Auto Negotiation Register AutngoChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Introduction Special 8b/10b Code GroupsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesThroughput Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsDSP Products ApplicationsRfid
Top Page Image Contents