Texas Instruments SPRU938B manual Read Performance, Throughput, Latency μsec

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Read Performance

B.3 Read Performance

Since reads must complete a transmit-remote read-receive cycle before starting another read transaction, the data throughput is lower as compared to writes. There is latency involved in reading the data from the remote device; and in some cases, a local latency in writing the returned data before the next read can start.

The max read rate is calculated the same way as the max write rate. The packet overhead is as shown below:

Read32 - caaaaT

ReadBurst - claaaaT

ReadReturn - clddddddddT

Where

T - EndOfPacket

d - data, dddd represents additional 32-bit words in burst, up to 16 words.

a - address

c - command

l - length

There are 6 bytes of overhead for a single read, 7 bytes for burst reads, and 3 bytes for read returns. The time required for a read is the total of the time for the read request, remote latency, read return, and local latency. Thus, the throughput can be calculated as data bytes/total transaction time, where the latency of both local and remote devices is combined.

Read Throughput = data/ (((Read + ReadReturn + data)/max read rate) + Latency

=(data × max read rate)/((Read + ReadReturn + data) + Latency × max read rate)

For example, with a 4 pin, 99 MHZ VLYNQ connection, for a single 32-bit word read:

Read Throughput = 32 bits × 316.8 Mbps/ (6 × 8 + 3 × 8 + 4 × 8 + Latency × 316.8Mbps)

= 10137.6/(104 + Latency × 316.8 Mbps)

Similarly, for a burst read of sixteen 32-bit words, with a 4 pin, 99 MHZ VLYNQ connection

Read Throughput = 16 × 32 bits × 316.8Mbps/(6 × 8 + 3 × 8 + 16 × 4 × 8 + Latency × 316.8Mbps) = 162201.6/(584 + Latency × 316.8Mbps)

Using the formula above, the relative performance with various latencies is illustrated for a 4 pin, 99 MHZ VLYNQ clock, burst read (sixteen 32-bit words) throughput rate, as shown in Table B-3.

Table B-3. Relative Performance with Various Latencies

Number of VLYNQ

Burst Size in

 

Throughput

Latency (μsec)

 

 

Pins (99 MHZ)

32-bit Words

Mbits/sec

Mbytes/sec

4

16

0

277.74

34.72

 

 

1

179.70

22.46

 

 

10

43.02

5.38

 

 

100

5.00

0.62

To efficiently use VLYNQ bandwidth, it is desirable for each VLYNQ device to write from the local device to the remote device. Burst transactions are more efficient than single read/write transactions.

46

Write/Read Performance

SPRU938B –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlPin Multiplexing Signal DescriptionsVlynq Signal Descriptions Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterEdma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Block Name Start Address End Address Size Vlynq Register Address SpaceVlynq Port Controller Registers Acronym Register DescriptionRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Supported Ordered Sets IntroductionSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secThroughput Read PerformanceTable B-3. Relative Performance with Various Latencies Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsDSP Products ApplicationsRfid
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