Texas Instruments SPRU938B manual Field Value Description

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VLYNQ 2.0 Packet Format

Table A-3. Packet Format (10-bit Symbol Representation) Description

Field

Value

Description

PKTTYPE[3:0]

 

This field indicates the packet type.

 

0000

Reserved

 

0001

Write with address increment.

 

0010

Reserved

 

0011

Write 32-bit word with address increment.

 

0100

Reserved

 

0101

Configuration write with address increment.

 

0110

Reserved for extended command indicator (cmd2)

 

0111

Interrupt

 

1000

Reserved

 

1001

Read with address increment.

 

1010

Reserved

 

1011

Read 32-bit word with address increment.

 

1100

Reserved

 

1101

Configuration read with address increment.

 

1110

Reserved for VLYNQ version 2.0 and later.

 

1111

Read response for all VLYNQ versions.

ADRMASK[3:0]

 

Indicates which byte of the address is included in the packet. Only address bytes that have changed

 

 

since the previous address will be included. Each bit corresponds to one byte of address.

BYTECNT[7:0]

 

Byte count. This field indicates the total number of bytes in the packet. This field is only included for

 

 

write, read, and configuration packet types. All other packet types have fixed lengths and do not

 

 

require this field.

ADDRESS[7:0]

 

Address byte 0. This byte is included only if ADRMASK[0] is set to 1. If ADRMASK[0] is cleared to 0,

 

 

assume this byte is equal to bits 7:0 of the previous address. Read response packets do not include

 

 

this field.

ADDRESS[15:8]

 

Address byte 1. This byte is included only if ADRMASK[1] is set to 1. If ADRMASK[1] is cleared to 0,

 

 

assume this byte is equal to bits 15:8 of the previous address. Read response packets do not include

 

 

this field.

ADDRESS[23:16]

 

Address byte 2. This byte is only included if ADRMASK[2] is set to 1. If ADRMASK[2] is cleared to 0,

 

 

this assume this byte is equal to bits 23:16 of the previous address. Read response packets do not

 

 

include this field.

ADDRESS[31:24]

 

Address byte 3. This byte is only included if ADRMASK[3] is set to 1. If ADRMASK[3] is cleared to 0,

 

 

assume this byte is equal to bits 31:24 of the previous address. Read response packets do not

 

 

include this field.

DATA

 

Data payload. The maximum data payload size is limited to sixteen 32-bit words to allow it to fit in the

 

 

RX FIFO.

EOP

 

End of packet indicator, /T/.

The CMD2 bit is only included in the packet, if the packet type indicates extended command (PKTTYPE = 0110).

Use configuration packet types to remotely access VLYNQ module registers. The configuration packet types do not depend on control register bit settings.

SPRU938B –September 2007

VLYNQ Protocol Specifications

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramVlynq Signal Descriptions Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramRemote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Vlynq Port Controller Registers Vlynq Register Address SpaceBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Special 8b/10b Code Groups IntroductionSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceThroughput Latency μsecReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryRfid Products ApplicationsDSP
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