Texas Instruments SPRU938B manual Address Translation Example Single Mapped Region

Page 17

www.ti.com

Peripheral Architecture

Figure 7. Example Address Memory Map

		Remote
	DMxxxdevice(local)	VLYNQdevice
		0000:0000h
		Mapregion1
	0400:0000h
	(4C00:0000hon
	DM643xdevice)	03FF:FFFFh
	Mapregion1	03FF:FFFFh
	Mapregion1	0400:0000h
		0400:0000h
		Mapregion2
	07FF:FFFFh	0400:00FFh
	0800:0000h
	Mapregion2
	0800:00FFh	0500:0000h
	0800:0100h
	Mapregion3	Mapregion3
	0801:00FFh	0500:FFFFh
	0801:0100h
	Mapregion4
		0B00:0000h
	0841:00FFh	Mapregion4
	0841:00FFh
		0B3F:FFFFh

The following shows an example illustrating the address translation used in each VLYNQ module. Address bits [31:26] are not used for address translation to remote devices on the DM643x device.

Table 2 shows the address map register configuration when the DM643x device is transmitting data to the remote device.

Table 2. Address Translation Example (Single Mapped Region)

Register	DM643x VLYNQ Module	Remote VLYNQ Module
TX Address Map	0000 : 0000h	Do not care
RX Address Map Size 1	Do not care	0000 : 0100h
RX Address Map Offset 1	Do not care	0800 : 0000h

SPRU938B –September 2007	VLYNQ Port	17
Submit Documentation Feedback

Image 17

Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramVlynq Signal Descriptions Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramRemote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Vlynq Port Controller Registers Vlynq Register Address SpaceBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Special 8b/10b Code Groups IntroductionSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceThroughput Latency μsecReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryRfid Products ApplicationsDSP