Texas Instruments SPRU938B manual Signal Descriptions, Pin Multiplexing, Protocol Description

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Peripheral Architecture

2.2Signal Descriptions

The VLYNQ module on the DM643x device supports 1 to 4 bit-wide RX/TX configurations. Chip-level pin multiplexing registers control the configuration. See the pin multiplexing information in the device-specific data manual.

If the VLYNQ data width does not match the number of transmit/receive lines that are available on the remote device, negotiation between the two VLYNQ devices automatically configures the width (see Section 2.7).

The VLYNQ interface signals are shown in Table 1.

Table 1. VLYNQ Signal Descriptions

Pin Name

Signal Name

Signal Type

Function

VLYNQ_CLOCK

VLYNQ serial clock

Input/Output

The VLYNQ reference clock supports the internally or

 

 

 

externally generated clock.

VLYNQ_SCRUN VLYNQ serial clock run Input/Output request (Active low)

The VLYNQ serial clock run request allows remote requests for the VLYNQ serial clock to be turned off for system power management.

Low: The request VLYNQ serial clock is active.

High: The VLYNQ serial clock is requested to be high when all transactions are complete.

VLYNQ_RXD[0:3]

VLYNQ receive data

Input

VLYNQ receive data is synchronous with the VLYNQ serial

 

 

 

clock.

VLYNQ_TXD[0:3]

VLYNQ transmit data

Output

VLYNQ transmit data is synchronous with the VLYNQ serial

 

 

 

clock.

2.3Pin Multiplexing

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configurations at device reset and software programmable register settings. The VLYNQ module pins are not enabled at reset. In order to change the default function of device pins at reset, the pin multiplexing registers (PINMUXn) must be configured appropriately. Refer to the pin multiplexing information in the device-specific data manual for more detailed information on the processor pin multiplexing and configuration registers.

2.4Protocol Description

VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allows for in-band packet delineation and control.

Appendix A provides general information on 8b/10b coding definitions and their implementation within the VLYNQ module in the DM643x device.

SPRU938B –September 2007

VLYNQ Port

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramProtocol Description Signal DescriptionsVlynq Signal Descriptions Pin MultiplexingVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlInterrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramRemote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Acronym Register Description Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address SizeBit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj RevminControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInstat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr NointpendIntset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field DescriptionsTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field DescriptionsVlynq Port Remote Controller Registers Table A-1. Special 8b/10b Code Groups IntroductionSpecial 8b/10b Code Groups Supported Ordered SetsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZLatency μsec Read PerformanceTable B-3. Relative Performance with Various Latencies ThroughputReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryRfid Products ApplicationsDSP
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