Texas Instruments SPRU938B manual List of Tables

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	List of Tables
1	VLYNQ Signal Descriptions	11
2	Address Translation Example (Single Mapped Region)	17
3	Address Translation Example (Single Mapped Region)	18
4	VLYNQ Register Address Space	24
5	VLYNQ Port Controller Registers	24
6	Revision Register (REVID) Field Descriptions	25
7	Control Register (CTRL) Field Descriptions	26
8	Status Register (STAT) Field Descriptions	28
9	Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions	30
10	Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions	30
11	Interrupt Pending/Set Register (INTPENDSET) Field Descriptions	31
12	Interrupt Pointer Register (INTPTR) Field Descriptions	31
13	Address Map Register (XAM) Field Descriptions	32
14	Receive Address Map Size 1 Register (RAMS1) Field Descriptions	33
15	Receive Address Map Offset 1 Register (RAMO1) Field Descriptions	33
16	Receive Address Map Size 2 Register (RAMS2) Field Descriptions	34
17	Receive Address Map Offset 2 Register (RAMO2) Field Descriptions	34
18	Receive Address Map Size 3 Register (RAMS3) Field Descriptions	35
19	Receive Address Map Offset 3 Register (RAMO3) Field Descriptions	35
20	Receive Address Map Size 4 Register (RAMS4) Field Descriptions	36
21	Receive Address Map Offset 4 Register (RAMO4) Field Descriptions	36
22	Chip Version Register (CHIPVER) Field Descriptions	37
23	Auto Negotiation Register (AUTNGO) Field Descriptions	37
24	VLYNQ Port Remote Controller Registers	38
A-1	Special 8b/10b Code Groups	39
A-2	Supported Ordered Sets	39
A-3	Packet Format (10-bit Symbol Representation) Description	41
B-1	Scaling Factors	45
B-2	Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ)	45
B-3	Relative Performance with Various Latencies	46
C-1	Document Revision History	47

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List of Tables

SPRU938B –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlPin Multiplexing Signal DescriptionsVlynq Signal Descriptions Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts Edma Event SupportRemote Interrupts Power Management Endianness ConsiderationsEmulation Considerations Block Name Start Address End Address Size Vlynq Register Address SpaceVlynq Port Controller Registers Acronym Register DescriptionRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Supported Ordered Sets IntroductionSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secThroughput Read PerformanceTable B-3. Relative Performance with Various Latencies Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsProducts Applications DSPRfid