Texas Instruments SPRU938B manual Vlynq 2.X Packets

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VLYNQ 2.X Packets

A.5 VLYNQ 2.X Packets

An example of what can happen to a write burst due to remote and local FIFO state changes and the link pulse timer expiring is shown in Example A-1. This protocol can be extended to apply to multiple channels; therefore, the data return channel is logically isolated from the command channel.

Example A-1. A write burst due to remote and local FIFO state changes and the link pulse timer expiring

Basic packets:

Read32 - caaaaT

Write32 - caaaaddddT

ReadCfg - claaaaT

WriteCfg - claaaaddddddddT

ReadBurst - claaaaT

WriteBurst - claaaaddddddddddddT

Int - cddddT

ReadReturn - clddddddddT

Where

I - Idle

T - EndOfPacket

d - data

a - address

c - command

l - length

M - Byte mask

I[#] - Flowed, # is used when exiting flowed for a channel, the # is actually the current channel command.

P# - Flow Enable for a channel

C# - Flow Disable for a channel L - Link pulse

and what is in italics is optional data up to 16 words total. Packet with byte enables:

WriteBurst - claaaaMMddMMddMMddT

The above packet wrote to the LS half words from the specified address. Packet that has been flowed due to remote FIFO status:

WriteBurst - claaaaMMddMIIIIIIIIIIIII#MddMMddT

The packet was extended using the I code. The # is used to indicate that the same channel was continued.

To the same packet, the potential flowing of the local FIFO’s is added: WriteBurst - claaaaMMddMIIP#IIIIIIIIIIIII#MddMMdC#dT

Link pulse to the stream is added:

WriteBurst - claaLaaMMddMIIP#IIIIIIIIIII#MddMMdC#dT

An example of a write burst flowed and interrupted by a read return data burst is shown below. In the example, a 1 indicates a data return channel (it is actually the return data command) and a 0 indicates a command channel, which is the command for the transaction.

IIIIclaaaaddddIcldddIII1ddddII0dddddddddddddIIIIII0dddTIIIII1dTIIII

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VLYNQ Protocol Specifications

SPRU938B –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlPin Multiplexing Signal DescriptionsVlynq Signal Descriptions Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts Edma Event SupportRemote Interrupts Power Management Endianness ConsiderationsEmulation Considerations Block Name Start Address End Address Size Vlynq Register Address SpaceVlynq Port Controller Registers Acronym Register DescriptionRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Supported Ordered Sets IntroductionSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secThroughput Read PerformanceTable B-3. Relative Performance with Various Latencies Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsProducts Applications DSPRfid