Texas Instruments SPRU938B manual Interrupt Pending/Set Register Intpendset, Intset

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VLYNQ Port Registers

3.6Interrupt Pending/Set Register (INTPENDSET)

The interrupt pending/set register (INTPENDSET) indicates the pending interrupt status when the INTLOCAL bit in the control register (CTRL) is not set. When the interrupt packet is forwarded on the serial interface, these bits are cleared. The INTPENDSET is shown in Figure 14 and described in Table 11.

Figure 14. Interrupt Pending/Set Register (INTPENDSET)

31

0

INTSET

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

Table 11. Interrupt Pending/Set Register (INTPENDSET) Field Descriptions

Bit	Field	Value	Description
31-0	INTSET	0-FFFF FFFFh	This field indicates the unmasked status of each pending interrupt.
		0	Writing a 0 has no effect.
		1	Writing a 1 to any bit:
			if INTLOCAL = 0 in CTRL, interrupt packet is sent on the serial interface.
			If INTLOCAL = 1 in CTRL, VLYNQ module interrupt (VLQINT) is asserted.

3.7Interrupt Pointer Register (INTPTR)

The interrupt pointer register (INTPTR) typically contains the address of the interrupt pending/set register (INTPENDSET) within the VLYNQ module. To program INTPTR to point to INTPENDSET, program a value of 14h (the offset of INTPENDSET). Additionally, the INT2CFG bit in the control register (CTRL) should be set to 1. The INTPTR is shown in Figure 15 and described in Table 12.

Figure 15. Interrupt Pointer Register (INTPTR)

31	2	1	0
INTPTR		Reserved
R/W-0			R-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 12. Interrupt Pointer Register (INTPTR) Field Descriptions

Bit	Field	Value	Description
31-2	INTPTR	0-3FFF FFFFh	Interrupt pointer. Program this register with the address (14h) of the interrupt pending/set
			register (INTPENDSET).
1-0	Reserved	0	Reserved. Always read as 0. Writes have no effect.

SPRU938B –September 2007	VLYNQ Port	31
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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramProtocol Description Signal DescriptionsVlynq Signal Descriptions Pin MultiplexingVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlInterrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramEdma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Acronym Register Description Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address SizeBit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj RevminControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInstat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr NointpendIntset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field DescriptionsAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field DescriptionsVlynq Port Remote Controller Registers Table A-1. Special 8b/10b Code Groups IntroductionSpecial 8b/10b Code Groups Supported Ordered SetsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZLatency μsec Read PerformanceTable B-3. Relative Performance with Various Latencies ThroughputReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryDSP Products ApplicationsRfid