Texas Instruments SPRU938B manual No error, Lerror

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VLYNQ Port Registers

Table 8. Status Register (STAT) Field Descriptions (continued)

Bit	Field	Value	Description
8	RERROR		Remote Error. Write a 1 to this bit to clear it.
		0	No error
		1	This bit indicates that a downstream VLYNQ module has detected a packet error. This bit is
		1	set when an error indication, /E/, is received from the serial interface. See Appendix A.

			If this bit is set, and the INTENABLE (bit 13 in VLYNQ control register) is also set, it asserts
			the VLYNQ interrupt (VLQINT).
7	LERROR		Local error. Write a 1 to this bit to clear it.
		0	No error.
		1	This bit indicates that an inbound packet contains an error that is detected by the local
		1	VLYNQ module.
			VLYNQ module.
			If this bit is set, and the INTENABLE (bit 13 in VLYNQ control register) is also set, it asserts
			the VLYNQ interrupt (VLQINT).
6	NFEMPTY3		FIFO 3 is not empty.
		0	Indicates that the slave command FIFO is empty.
		1	Indicates that the slave command FIFO is not empty.
5	NFEMPTY2		FIFO 2 is not empty.
		0	Indicates that the slave data FIFO is empty.
		1	Indicates that the slave data FIFO is not empty.
4	NFEMPTY1		FIFO 1 is not empty.
		0	Indicates that the master command FIFO is empty.
		1	Indicates that the master command FIFO is not empty.
3	NFEMPTY0		FIFO 0 is not empty.
		0	Indicates that the master data FIFO is empty.
		1	Indicates that the master data FIFO is not empty.
2	SPEND		Pending slave request.
		0	No pending slave requests.
		1	Indicates detection of a transfer request initiated by the VLYNQ module to the off-chip
		1	peripheral (TX slave configuration bus interface).
			peripheral (TX slave configuration bus interface).
1	MPEND		Pending master requests.
		0	No pending master requests.
		1	Indicates detection of a transfer request initiated by an off-chip peripheral to the VLYNQ
		1	module (RX master configuration bus interface).
			module (RX master configuration bus interface).
0	LINK		Link
		0	Indicates that the serial interface initialization sequence has not yet completed or the link
			has timed out.
		1	Indicates that the serial interface initialization sequence has completed successfully.

SPRU938B –September 2007	VLYNQ Port	29
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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramVlynq Signal Descriptions Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramRemote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Vlynq Port Controller Registers Vlynq Register Address SpaceBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Special 8b/10b Code Groups IntroductionSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceThroughput Latency μsecReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryRfid Products ApplicationsDSP