Texas Instruments SPRU938B Receive Address Map Size 2 Register RAMS2, RXADRSIZE2, RXADROFFSET2

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VLYNQ Port Registers

3.11 Receive Address Map Size 2 Register (RAMS2)

The receive address map size 2 register (RAMS2) is used to identify the intended destination of inbound serial packets. The RAMS2 is shown in Figure 19 and described in Table 16.

Figure 19. Receive Address Map Size 2 Register (RAMS2)

31

2

1

0

RXADRSIZE2

 

Reserved

R/W-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

Table 16. Receive Address Map Size 2 Register (RAMS2) Field Descriptions

Bit

Field

Value

Description

31-2

RXADRSIZE2

0-3FFF FFFFh

The RXADRSIZE2 field is used to determine if receive packets are destined for the second

 

 

 

of four mapped address regions. RXADRSIZE2 is compared with the address contained in

 

 

 

the receive packet. If the received packet address is less than the value in RXADRSIZE2,

 

 

 

the packet address is added to the receive address map offset 2 register (RAMO2) to obtain

 

 

 

the translated address.

1-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

3.12 Receive Address Map Offset 2 Register (RAMO2)

The receive address map offset 2 register (RAMO2) is used with the receive address map size 2 register (RAMS2) to translate receive packet addresses to local device configuration bus addresses. The RAMO2 is shown in Figure 20 and described in Table 17.

Figure 20. Receive Address Map Offset 2 Register (RAMO2)

31

2

1

0

RXADROFFSET2

 

Reserved

R/W-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

Table 17. Receive Address Map Offset 2 Register (RAMO2) Field Descriptions

Bit

Field

Value

Description

31-2

RXADROFFSET2

0-3FFF FFFFh

The RXADROFFSET2 field is used with the receive address map size 2 register (RAMS2)

 

 

 

to determine the translated address for serial data. If the received packet address is less

 

 

 

than the value in RAMS2, the packet address is added to the contents of this register to

 

 

 

obtain the translated address.

1-0

Reserved

0

Reserved. Always read as 0. Writes have no affect.

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VLYNQ Port

SPRU938B –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlPin Multiplexing Signal DescriptionsVlynq Signal Descriptions Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterEdma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Block Name Start Address End Address Size Vlynq Register Address SpaceVlynq Port Controller Registers Acronym Register DescriptionRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Supported Ordered Sets IntroductionSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secThroughput Read PerformanceTable B-3. Relative Performance with Various Latencies Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsDSP Products ApplicationsRfid
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