Texas Instruments SPRU938B manual Burst Size Interface Running at 76.5 MHZ

Page 45

www.ti.com

			Write Performance
	Table B-1. Scaling Factors
Burst Size in 32-bit words	Data Bytes	Overhead Bytes	Scaling Factor
1	4	6	40%
4	16	7	69.56%
8	32	7	82.05%
16	64	7	90.14%

Table B-2. Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ)

	Burst Size in	Interface Running at 76.5 MHZ		Interface Running at 99 MHZ
	Burst Size in
Number of VLYNQ Pins	32-bit Words	Mbits/sec	Mbytes/sec	Mbits/sec	Mbytes/sec
1	1	24.19	3.02	31.68	3.96
	4	42.07	5.26	55.09	6.89
	8	49.62	6.20	64.98	8.12
	16	54.52	6.81	71.39	8.92
2	1	48.38	6.05	63.36	7.92
	4	84.14	10.52	110.18	13.77
	8	99.25	12.41	129.97	16.25
	16	109.03	13.63	142.78	17.85
3	1	72.58	9.07	95.04	11.88
	4	126.21	15.78	165.27	20.66
	8	148.87	18.61	194.95	24.37
	16	163.55	20.44	214.17	26.77
4	1	96.77	12.10	126.72	15.84
	4	168.28	21.03	220.37	27.55
	8	198.50	24.81	259.93	32.49
	16	218.07	27.26	285.56	35.70

SPRU938B –September 2007	Write/Read Performance	45
Submit Documentation Feedback

Image 45

Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramVlynq Signal Descriptions Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramSerial Bus Error Interrupts Edma Event SupportRemote Interrupts Power Management Endianness ConsiderationsEmulation Considerations Vlynq Port Controller Registers Vlynq Register Address SpaceBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Special 8b/10b Code Groups IntroductionSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceThroughput Latency μsecReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryProducts Applications DSPRfid