Texas Instruments SPRU938B manual Write Operations

Page 13

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Peripheral Architecture

2.5.1Write Operations

Write requests that initiate from the slave configuration bus interface of the local device write to the outbound command (CMD) FIFO. Data is subsequently read from the FIFO and encapsulated in a write request packet. The address is translated, and the packet is encoded and serialized before being transmitted to remote device. The remote device subsequently deserializes and decodes the receive data and writes it into the inbound CMD FIFO. A write operation initiates on the remote device’s master configuration bus interface after reading the address and data from the FIFO.

The data flow between two VLYNQs that are connected is shown in Figure 5. In the example shown in Figure 5, the write originates from the DM643x device.

Figure 5. Write Operations

 

 

System￿clock

 

VLYNQ￿clock

 

 

 

 

 

 

 

 

 

 

Serial

Slave

Address

Outbound

Outbound

 

8B/10B

 

TxData

config￿bus

command

TxSM

Serializer

 

translation

commands

encoding

 

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

Registers

 

 

 

Local￿VLYNQ

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

Master

Address

Inbound

Inbound

 

8B/10B

 

Serial

config￿bus

command

RxSM

Deserializer

translation

commands

decoding

RxData

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System￿clock

 

VLYNQ￿Clock

 

 

 

 

 

 

 

 

 

 

Serial

Slave

Address

Outbound

Outbound

 

8B/10B

 

TxData

config￿bus

 

 

command

TxSM

Serializer

 

translation

commands

encoding

 

interface

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

Registers

 

 

 

Remote￿VLYNQ

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

Serial

Master

Address

Inbound

Inbound

 

8B/10B

 

RxData

config￿bus

command

RxSM

Deserializer

 

translation

commands

decoding

 

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPRU938B –September 2007

VLYNQ Port

13

Image 13
Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramVlynq Signal Descriptions Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramEdma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Vlynq Port Controller Registers Vlynq Register Address SpaceBlock Name Start Address End Address Size Acronym Register DescriptionRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Special 8b/10b Code Groups IntroductionSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceThroughput Latency μsecReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryDSP Products ApplicationsRfid