Texas Instruments SPRU938B manual Vlynq Port Remote Controller Registers

Page 38

www.ti.com

Remote Configuration Registers

4Remote Configuration Registers

The remote configuration registers listed in Table 24 are the same registers as previously described, but they are for the remote VLYNQ device.

Note: Before attempting to access the remote registers (offsets 80h through C0h) , you must ensure that a link is established with the remote device. Poll the LINK bit in the VLYNQ status register (STAT) to do this.

It is not necessary to configure the address translation registers to access the remote device'smemory-mapped registers after the link has been established.

Depending on the version and chip specific implementation, the VLYNQ module on the remote device might have additional registers or different reset values. Refer to the remote device data sheet for a precise description of the VLYNQ registers that exist in the remote device.

	Table 24. VLYNQ Port Remote Controller Registers
Offset	Acronym	Register Description
80h	RREVID	Remote Revision Register
84h	RCTRL	Remote Control Register
88h	RSTAT	Remote Status Register
8Ch	RINTPRI	Remote Interrupt Priority Vector Status/Clear Register
90h	RINTSTATCLR	Remote Interrupt Status/Clear Register
94h	RINTPENDSET	Remote Interrupt Pending/Set Register
98h	RINTPTR	Remote Interrupt Pointer Register
9Ch	RXAM	Remote Transmit Address Map Register
A0h	RRAMS1	Remote Receive Address Map Size 1 Register
A4h	RRAMO1	Remote Receive Address Map Offset 1 Register
A8h	RRAMS2	Remote Receive Address Map Size 2 Register
ACh	RRAMO2	Remote Receive Address Map Offset 2 Register
B0h	RRAMS3	Remote Receive Address Map Size 3 Register
B4h	RRAMO3	Remote Receive Address Map Offset 3 Register
B8h	RRAMS4	Remote Receive Address Map Size 4 Register
BCh	RRAMO4	Remote Receive Address Map Offset 4 Register
C0h	RCHIPVER	Remote Chip Version Register
C4h	RAUTNGO	Remote Auto Negotiation Register
C8h	RMANNGO	Remote Manual Negotiation Register
CCh	RNGOSTAT	Remote Negotiation Status Register
E0h	RINTVEC0	Remote Interrupt Vector 3-0 Register
E4h	RINTVEC1	Remote Interrupt Vector 7-4 Register

38

VLYNQ Port

SPRU938B –September 2007

Submit Documentation Feedback

Image 38

Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlPin Multiplexing Signal DescriptionsVlynq Signal Descriptions Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterRemote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Block Name Start Address End Address Size Vlynq Register Address SpaceVlynq Port Controller Registers Acronym Register DescriptionRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Supported Ordered Sets IntroductionSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secThroughput Read PerformanceTable B-3. Relative Performance with Various Latencies Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsRfid Products ApplicationsDSP