Texas Instruments SPRU938B Receive Address Map Size 3 Register RAMS3, RXADRSIZE3, RXADROFFSET3

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VLYNQ Port Registers

3.13 Receive Address Map Size 3 Register (RAMS3)

The receive address map size 3 register (RAMS3) is used to identify the intended destination of inbound serial packets. The RAMS3 is shown in Figure 21 and described in Table 18.

Figure 21. Receive Address Map Size 3 Register (RAMS3)

31

2

1

0

RXADRSIZE3

 

Reserved

R/W-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

Table 18. Receive Address Map Size 3 Register (RAMS3) Field Descriptions

Bit

Field

Value

Description

31-2

RXADRSIZE3

0-3FFF FFFFh

The RXADRSIZE3 field is used to determine if receive packets are destined for the third of

 

 

 

four mapped address regions. RXADRSIZE3 is compared with the address contained in the

 

 

 

receive packet. If the receive packet address is less than the value in RXADRSIZE3, the

 

 

 

packet address is added to the receive address map offset 3 register (RAMO3) to obtain the

 

 

 

translated address.

1-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

3.14 Receive Address Map Offset 3 Register (RAMO3)

The receive address map offset 3 register (RAMO3) is used with the receive address map size 3 register (RAMS3) to translate receive packet addresses to local device configuration bus addresses. The RAMO3 is shown in Figure 22 and described in Table 19.

Figure 22. Receive Address Map Offset 3 Register (RAMO3)

31

2

1

0

RXADROFFSET3

 

Reserved

R/W-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

Table 19. Receive Address Map Offset 3 Register (RAMO3) Field Descriptions

Bit

Field

Value

Description

31-2

RXADROFFSET3

0-3FFF FFFFh

The RXADROFFSET3 field is used with the receive address map size 3 register (RAMS3)

 

 

 

to determine the translated address for serial data. If the receive packet address is less

 

 

 

than the value in RAMS3, the packet address is added to the contents of this register to

 

 

 

obtain the translated address.

1-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

SPRU938B –September 2007

VLYNQ Port

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramClock Control External Clock Block DiagramProtocol Description Signal DescriptionsVlynq Signal Descriptions Pin MultiplexingVlynq Module Structure Vlynq Functional DescriptionWrite Operations Read Operations Auto-Negotiation InitializationAddress Translation Register DM643x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM643x Vlynq ModuleExample 1. Address Translation Example Flow ControlInterrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramRemote Interrupts Serial Bus Error InterruptsEdma Event Support Emulation Considerations Power ManagementEndianness Considerations Acronym Register Description Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address SizeBit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj RevminControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInstat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr NointpendIntset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field DescriptionsTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field DescriptionsVlynq Port Remote Controller Registers Table A-1. Special 8b/10b Code Groups IntroductionSpecial 8b/10b Code Groups Supported Ordered SetsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Bit Words Mbits/sec Mbytes/sec Burst Size Interface Running at 76.5 MHZLatency μsec Read PerformanceTable B-3. Relative Performance with Various Latencies ThroughputReference Additions/Modifications/Deletions Table C-1. Document Revision HistoryRfid Products ApplicationsDSP
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