Texas Instruments SPRU938B manual DM643x Vlynq Module, Remote Vlynq Module

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Peripheral Architecture

DM643x VLYNQ Module:

	4C00 : 0054h	Initial address at the slave configuration bus
	0000 : 0054h	Initial address [25:0] at the slave configuration bus interface
subtract	0000 : 0000h	TX address map register (there is no need to change the reset value of the
		DM643x device for this register)
	0000 : 0054h
Remote VLYNQ Module:
	0000 : 0054h	Initial address from the RX serial interface
compare	0000 : 0100h	RX address map size 1 register
	0000 : 0054h
add	0800 : 0000h	RX address map offset 1 register
	0800 : 0054h	Translated address to remote device

The local address 4C00:0054h (or 0000 0054h) was translated to 0800:0054h on the remote VLYNQ device in Table 3.

Table 3 shows the address map register configuration when the DM643x device is receiving data from the remote device.

Table 3. Address Translation Example (Single Mapped Region)

Register	DM643x VLYNQ Module	Remote VLYNQ Module
TX Address Map	Do not care	0400 : 0000h
RX Address Map Size 1	0000 : 0100h	Do not care
RX Address Map Offset 1	0200 : 0000h	Do not care
RX Address Map Size 2	0000 : 0100h	Do not care
RX Address Map Offset 2	8200 : 0000h	Do not care

Remote VLYNQ Module:

		0400 : 0154h Initial address at the slave configuration bus for the remote device
subtract		0400 : 0000h TX address map register
		0000 : 0154h Translated address to remote device via serial interface
DM643x VLYNQ Module:
		0000 : 0154h Initial address from the RX serial interface
compare		0000 : 0100h RX address map size 1 register
		0000 : 0154h The RX packet address is greater than the value in the RX address map size 1
		register
compare		0000 : 0200h RX address map size 1 register + RX address map size 2
		Since the RX packet address < the RX address map size 1 register +
		RX address map size 2 register
add		8200 : 0000h RX address map offset 2 register
subtract		0000 : 0100h RX address map size 1 register
		8200 : 0054h Translated address to DM643x device
18	VLYNQ Port	SPRU938B –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlPin Multiplexing Signal DescriptionsVlynq Signal Descriptions Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts Edma Event SupportRemote Interrupts Power Management Endianness ConsiderationsEmulation Considerations Block Name Start Address End Address Size Vlynq Register Address SpaceVlynq Port Controller Registers Acronym Register DescriptionRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Supported Ordered Sets IntroductionSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secThroughput Read PerformanceTable B-3. Relative Performance with Various Latencies Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsProducts Applications DSPRfid