Texas Instruments SPRU938B Edma Event Support, Remote Interrupts, Serial Bus Error Interrupts

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Peripheral Architecture

2.11.3Remote Interrupts

Remote interrupts occur when an interrupt packet is received over the serial interface from a remote device. The interrupt status is extracted from the packet and written to a location pointed to by the interrupt pointer register (INTPTR).

The INTPTR should contain the address of the interrupt pending/set register (INTPENDSET). To get INTPTR to contain the address of INTPENDSET, program INTPTR with a value of 14h (the offset for INTPENDSET). Additionally, the INT2CFG bit in the VLYNQ control register (CTRL) must be set to 1, dictating that the VLYNQ writes to a local register space (in this case, INTPENDSET).

Once an interrupt packet is received over the serial interface, the interrupt status is extracted and written to INTPENDSET. After the interrupt status is extracted and written to INTPENDSET, the interrupt generation occurs as previously described in Section 2.11.2.

The following summarizes the steps that are required to ensure that the device receives the remote interrupts:

∙Program the VLYNQ interrupt pointer register (INTRPTR) with a value of 14h, which is the offset address of the VLYNQ interrupt/pending set register (INTPENDSET).

∙Set the INT2CFG bit to 1 in the VLYNQ control register (CTRL).

2.11.4Serial Bus Error Interrupts

Due to erroneous transmit packets that are detected by remote devices (remote error) or errors in the inbound packets (local error), the serial bus errors result in the setting of the RERROR or LERROR bits in the VLYNQ status register (STAT).

Additionally, if the INTENABLE bit is set in the VLYNQ control register (CTRL), setting the RERROR or LERROR bits cause these status interrupts to post to the interrupt pending/set register (INTPENDSET), causing the VLYNQINT to be asserted to the CPU.

To ensure that serial bus errors result in interrupts to notify the application software, you must perform the following steps:

1.Set the INTENABLE bit to 1 in the VLYNQ control register (CTRL).

2.Set the INTVEC bits in CTRL to point to a free bit in the VLYNQ interrupt pending/set register (INTPENDSET). The serial bus error should result in setting the bits in INTPENDSET that are not used by the application software for other interrupts (bit locations written directly in INTPENDSET or via remote interrupts).

3.During VLYNQ initialization, the RERROR bit is set after the VLYNQ module achieves a link. When the link bit is set in the VLYNQ status register (STAT), write a 1 to the RERROR bit. Writing a 1 to the RERROR bit clears the RERROR bit and prevents the software interrupt handler from seeing the first RERROR as a legitimate serial bus error interrupt.

2.12EDMA Event Support

The VLYNQ module on the DM643x device is classified as a master peripheral. Classification as a master peripheral normally implies that the peripheral is able to sustain its own transfers without relying on any external peripherals (for example, the system DMA, etc). However, the VLYNQ module does not have an internal DMA (as some other master peripherals).

Therefore, it is likely that the VLYNQ module can rely on the on-chip enhanced DMA (EDMA3) controller for performing burst transfer. The EDMA3 can still be used to perform burst transfers out to remote VLYNQ memory map (writes). This use model provides better throughput with less overhead.

Note: There is no VLYNQ event that allows hardware synchronization to occur with the EDMA3 controller on the DM643x device.

The VLYNQ module uses a 16-word deep FIFO to buffer the burst writes. Since the EDMA3 controller is much faster compared to the serial VLYNQ interface, a data back-up can occur. Therefore, configuring EDMA3 for optimal transfer size, etc. is essential.

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VLYNQ Port

SPRU938B –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Industry Standards Compliance StatementExternal Clock Block Diagram Clock ControlPin Multiplexing Signal DescriptionsVlynq Signal Descriptions Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations Read Operations Initialization Auto-NegotiationAddress Translation Address Translation Example Single Mapped Region Register DM643x Vlynq ModuleDM643x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterEdma Event Support Serial Bus Error InterruptsRemote Interrupts Endianness Considerations Power ManagementEmulation Considerations Block Name Start Address End Address Size Vlynq Register Address SpaceVlynq Port Controller Registers Acronym Register DescriptionRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Supported Ordered Sets IntroductionSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Burst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secThroughput Read PerformanceTable B-3. Relative Performance with Various Latencies Latency μsecTable C-1. Document Revision History Reference Additions/Modifications/DeletionsDSP Products ApplicationsRfid
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