Analog Devices ADSP-TS201S specifications Pin Definitions-External Port DMA/Flyby, Makes

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ADSP-TS201S

Table 7. Pin Definitions—External Port DMA/Flyby

Signal

Type

Term

Description

I/A

epu

DMA Request Pins. Enable external I/O devices to request DMA services from the DSP.

DMAR3–0

In response to

DMARx,

the DSP performs DMA transfers according to the DMA

channel’s initialization. The DSP ignores DMA requests from uninitialized channels.

O/T

nc

I/O Write. When a DSP DMA channel initiates a flyby mode read transaction, the DSP

IOWR

(pu_0)

asserts the

IOWR

signal during the data cycles. This assertion makes the I/O device

sample the data instead of the TigerSHARC.

O/T

nc

I/O Read. When a DSP DMA channel initiates a flyby mode write transaction, the DSP

IORD

(pu_0)

asserts the

IORD

signal during the data cycle. This assertion with the

IOEN

makes the

I/O device drive the data instead of the TigerSHARC.

O/T

nc

I/O Device Output Enable. Enables the output buffers of an external I/O device for fly-

IOEN

(pu_0)

by transactions between the device and external memory. Active on flyby

transactions.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

Rev. C Page 15 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S FIR filter per real tap 83 ns General-Purpose Algorithm Benchmarks at 600 MHzClock Benchmark Speed CyclesDual Compute Blocks Data Alignment Buffer DABDual Integer ALU Ialu Flexible Instruction Set Program SequencerDSP Memory Interrupt ControllerInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceSdram Controller DMA ControllerHost Interface Multiprocessor InterfaceDMA controller provides these additional features Link Ports Lvds Timer and GENERAL-PURPOSE I/OReset and Booting No Boot, Run from Memory AddressesPower Domains Filtering Reference Voltage and ClocksDevelopment Tools Additional Information Evaluation KITRatio Pin Definitions-Clocks and ResetSignal Type Term Description Sclk RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeMakes Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA Sample the data instead of the TigerSHARCSDA10 Pin Definitions-External Port Sdram ControllerLdqm HdqmPin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerDS1 Pin Definitions-Link PortsCONTROLIMP0 CONTROLIMP1Impedance Control Selection Pin Definitions-Power, Ground, and ReferenceDriver Mode DS2-0 Drive Output Pins Strength ImpedancePin Definitions-I/O Strap Pins Type at Signal ResetPin Rstin = Sclkvref Operating ConditionsVIN Max VIN Min Cycle2 Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage Maximum DutyPackage Brand Information Package InformationESD Sensitivity Absolute Maximum RatingsReference Clocks-Core Clock Cclk Cycle Time Timing SpecificationsAC Asynchronous Signal Specifications General AC TimingParameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Sclkrat = 5⋅, 7⋅ Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap SYS 9 DS2-0 Static Pins-Must Be ConstantStrap Pins Jtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0VOD Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Parameter Condition Typical Unit Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Environmental ConditionsBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0DATI3N Sdcke SCLKRAT1L0ACKO L0DATI1NL1CLKINN DS2 Enedreg TCKID2 TDI TMR0E DS1 CONTROLIMP1 TDO FLAG3Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Surface Mount DesignBGA Data for Use with Surface Mount Design Package Ball Attach Type Solder Mask Opening Ball Pad SizeTemperature Instruction On-Chip Package Model Range1 Rate2 Ordering GuideOperating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December