Analog Devices ADSP-TS201S specifications

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TigerSHARC®

a

Embedded Processor

 

 

 

ADSP-TS201S

 

 

KEY FEATURES

Up to 600 MHz, 1.67 ns instruction cycle rate

24M bits of internal—on-chip—DRAM memory

25 mm × 25 mm (576-ball) thermally enhanced ball grid array package

Dual-computation blocks—each containing an ALU, a multiplier, a shifter, a register file, and a communications logic unit (CLU)

Dual-integer ALUs, providing data addressing and pointer manipulation

Integrated I/O includes 14-channel DMA controller, external port, four link ports, SDRAM controller, programmable flag pins, two timers, and timer expired pin for system integration

1149.1 IEEE-compliant JTAG test access port for on-chip emulation

Single-precision IEEE 32-bit and extended-precision 40-bit floating-point data formats and 8-, 16-, 32-, and 64-bit fixed-point data formats

KEY BENEFITS

Provides high performance static superscalar DSP operations, optimized for telecommunications infrastructure and other large, demanding multiprocessor DSP applications

Performs exceptionally well on DSP algorithm and I/O benchmarks (see benchmarks in Table 1)

Supports low overhead DMA transfers between internal memory, external memory, memory-mapped peripherals, link ports, host processors, and other (multiprocessor) DSPs

Eases DSP programming through extremely flexible instruc- tion set and high-level-language-friendly DSP architecture

Enables scalable multiprocessing systems with low commu- nications overhead

Provides on-chip arbitration for glueless multiprocessing

DATA ADDRESS GENERATION

24M BITS INTERNAL MEMORY

SOC BUS

JTAG PORT

 

 

INTEGER

32

32

INTEGER

 

 

MEMORY BLOCKS

 

 

JTAG

6

 

 

 

 

 

 

 

 

 

 

 

 

 

J ALU

 

 

K ALU

 

 

 

(PAGE CACHE)

 

 

 

 

 

 

 

 

 

 

 

 

 

EXTERNAL

 

 

32-BIT × 32-BIT

32-BIT × 32-BIT

 

4 × CROSSBAR CONNECT

 

PROGRAM

 

 

 

 

PORT

 

SEQUENCER

 

 

 

 

 

 

 

A

D A D

A D A D

 

 

 

32

 

ADDR

J-BUS ADDR

 

 

 

 

 

32

 

 

HOST

ADDR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64

 

FETCH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MULTI-

DATA

 

J-BUS DATA

 

 

 

 

 

128

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PROC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDRAM

8

CTRL

 

K-BUS ADDR

 

 

 

 

 

32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CTRL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BTB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C-BUS

10

CTRL

K-BUS DATA

 

 

 

 

 

128

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ARB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I-BUS ADDR

 

 

 

 

 

32

 

 

 

 

SOC

 

EXT DMA

 

 

 

 

 

 

 

 

 

 

I/F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

128

 

 

 

 

 

 

 

REQ

4

PC

I-BUS DATA

 

 

 

 

 

 

 

 

 

 

 

DMA

 

 

 

 

 

 

 

 

 

 

 

 

S-BUS ADDR

 

21

 

LINK PORTS

 

T

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IN

8

 

 

 

 

 

 

S-BUS DATA

128

 

 

L0

4

 

IAB

 

 

 

 

 

 

OUT

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IN

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L1

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUT

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IN

8

 

 

 

 

 

 

128

 

 

128

 

 

 

 

 

 

L2

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUT

8

 

 

 

 

 

X

 

 

 

 

 

Y

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IN

8

 

 

 

 

REGISTER

128

 

 

128

REGISTER

 

 

 

 

 

CLU

SHIFT

ALU MUL

 

 

MUL

ALU

SHIFT

CLU

L3

4

 

 

FILE

 

DAB

DAB

 

 

FILE

 

 

 

 

 

 

 

 

 

 

 

 

OUT

8

 

 

 

 

32-BIT × 32-BIT

 

 

 

32-BIT × 32-BIT

 

 

 

 

 

 

COMPUTATIONAL BLOCKS

Figure 1. Functional Block Diagram

TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700www.analog.com

Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

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Contents ADSP-TS201S ADSP-TS201S Clock General-Purpose Algorithm Benchmarks at 600 MHzBenchmark Speed Cycles FIR filter per real tap 83 nsData Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu DSP Memory Program SequencerInterrupt Controller Flexible Instruction SetInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceHost Interface DMA ControllerMultiprocessor Interface Sdram ControllerDMA controller provides these additional features Reset and Booting Timer and GENERAL-PURPOSE I/ONo Boot, Run from Memory Addresses Link Ports LvdsFiltering Reference Voltage and Clocks Power DomainsDevelopment Tools Additional Information Evaluation KITSignal Type Term Description Pin Definitions-Clocks and ResetSclk Ratio RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeDSP performs DMA transfers according to the DMA Pin Definitions-External Port DMA/FlybySample the data instead of the TigerSHARC MakesLdqm Pin Definitions-External Port Sdram ControllerHdqm SDA10Pin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerCONTROLIMP0 Pin Definitions-Link PortsCONTROLIMP1 DS1Driver Mode Pin Definitions-Power, Ground, and ReferenceDS2-0 Drive Output Pins Strength Impedance Impedance Control SelectionType at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Sclkvref Operating ConditionsMaximum Duty Cycle for Input Transient Voltage Electrical CharacteristicsMaximum Duty VIN Max VIN Min Cycle2ESD Sensitivity Package InformationAbsolute Maximum Ratings Package Brand InformationAC Asynchronous Signal Specifications Timing SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Reference Clocks-System Clock Sclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap Pins DS2-0 Static Pins-Must Be ConstantJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9Link Port Lvds Receive Electrical Characteristics Link Port Lvds Transmit Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VODParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Thermal Characteristics for 25 mm × 25 mm Package Thermal CharacteristicsEnvironmental Conditions Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0ACKO Sdcke SCLKRAT1L0DATI1N L0DATI3NID2 TDI TMR0E DS2 Enedreg TCKDS1 CONTROLIMP1 TDO FLAG3 L1CLKINNBGA Data for Use with Surface Mount Design Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Ordering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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