Analog Devices ADSP-TS201S specifications Reference Clocks-System Clock Sclk Cycle Time

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ADSP-TS201S

Table 23. Reference Clocks—System Clock (SCLK) Cycle Time

		SCLKRAT = 4⋅, 6⋅, 8⋅, 10⋅, 12⋅		SCLKRAT = 5⋅, 7⋅
Parameter	Description	Min	Max	Min	Max	Unit
1, 2, 3	System Clock Cycle Time	8	50	8	50	ns
tSCLK	System Clock Cycle Time	8	50	8	50	ns
tSCLKH	System Clock Cycle High Time	0.40 × tSCLK	0.60 × tSCLK	0.45 × tSCLK	0.55 × tSCLK	ns
tSCLKL	System Clock Cycle Low Time	0.40 × tSCLK	0.60 × tSCLK	0.45 × tSCLK	0.55 × tSCLK	ns
tSCLKF	System Clock Transition Time—Falling Edge4	—	1.5	—	1.5	ns
tSCLKR	System Clock Transition Time—Rising Edge	—	1.5	—	1.5	ns
5, 6	System Clock Jitter Tolerance	—	500	—	500	ps
tSCLKJ	System Clock Jitter Tolerance	—	500	—	500	ps

1For more information, see Table 3 on Page 12.

2For more information, see Clock Domains on Page 9.

3The value of (tSCLK / SCLKRAT2-0) must not violate the specification for tCCLK.

4 System clock transition times apply to minimum SCLK cycle time (tSCLK) only.

5 Actual input jitter should be combined with ac specifications for accurate timing analysis. 6 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

SCLK

tSCLK

tSCLKH tSCLKL

tSCLKJ tSCLKF tSCLKR

Figure 10. Reference Clocks—System Clock (SCLK) Cycle Time

Table 24. Reference Clocks—JTAG Test Clock (TCK) Cycle Time

Parameter	Description	Min	Max	Unit
tTCK	Test Clock (JTAG) Cycle Time	Greater of 30 or tCCLK × 4	—	ns
tTCKH	Test Clock (JTAG) Cycle High Time	12	—	ns
tTCKL	Test Clock (JTAG) Cycle Low Time	12	—	ns

tTCK

tTCKH

tTCKL

TCK

Figure 11. Reference Clocks—JTAG Test Clock (TCK) Cycle Time

Rev. C Page 25 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S Clock General-Purpose Algorithm Benchmarks at 600 MHzBenchmark Speed Cycles FIR filter per real tap 83 nsData Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu DSP Memory Program SequencerInterrupt Controller Flexible Instruction SetInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceHost Interface DMA ControllerMultiprocessor Interface Sdram ControllerDMA controller provides these additional features Reset and Booting Timer and GENERAL-PURPOSE I/ONo Boot, Run from Memory Addresses Link Ports LvdsFiltering Reference Voltage and Clocks Power DomainsDevelopment Tools Additional Information Evaluation KITSignal Type Term Description Pin Definitions-Clocks and ResetSclk Ratio RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeDSP performs DMA transfers according to the DMA Pin Definitions-External Port DMA/FlybySample the data instead of the TigerSHARC MakesLdqm Pin Definitions-External Port Sdram ControllerHdqm SDA10Pin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerCONTROLIMP0 Pin Definitions-Link PortsCONTROLIMP1 DS1Driver Mode Pin Definitions-Power, Ground, and ReferenceDS2-0 Drive Output Pins Strength Impedance Impedance Control SelectionType at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Sclkvref Operating ConditionsMaximum Duty Cycle for Input Transient Voltage Electrical CharacteristicsMaximum Duty VIN Max VIN Min Cycle2ESD Sensitivity Package InformationAbsolute Maximum Ratings Package Brand InformationAC Asynchronous Signal Specifications Timing SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Reference Clocks-System Clock Sclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap Pins DS2-0 Static Pins-Must Be ConstantJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9Link Port Lvds Receive Electrical Characteristics Link Port Lvds Transmit Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VODParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Thermal Characteristics for 25 mm × 25 mm Package Thermal CharacteristicsEnvironmental Conditions Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0ACKO Sdcke SCLKRAT1L0DATI1N L0DATI3NID2 TDI TMR0E DS2 Enedreg TCKDS1 CONTROLIMP1 TDO FLAG3 L1CLKINNBGA Data for Use with Surface Mount Design Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Ordering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December