Analog Devices ADSP-TS201S Pin Definitions-Link Ports, CONTROLIMP0, CONTROLIMP1, DS1, Enedreg

Page 18

ADSP-TS201S

Table 11. Pin Definitions—Link Ports

 

Signal

Type

Term

Description

 

 

LxDATO3–0P

O

nc

Link Ports 3–0 Data 3–0 Transmit LVDS P

 

 

LxDATO3–0N

O

nc

Link Ports 3–0 Data 3–0 Transmit LVDS N

 

 

LxCLKOUTP

O

nc

Link Ports 3–0 Transmit Clock LVDS P

 

 

LxCLKOUTN

O

nc

Link Ports 3–0 Transmit Clock LVDS N

 

 

LxACKI

I (pd)

nc

Link Ports 3–0 Receive Acknowledge. Using this signal, the receiver indicates to the

 

 

 

 

 

 

 

transmitter that it may continue the transmission.

 

 

 

 

 

O (pu)

nc

Link Ports 3–0 Block Completion. When the transmission is executed using DMA, this

 

 

LxBCMPO

 

 

 

 

 

 

 

signal indicates to the receiver that the transmitted block is completed. The pull-up

 

 

 

 

 

 

 

resistor is present on

L0BCMPO

only. At reset, the

L1BCMPO,

 

L2BCMPO,

and

L3BCMPO

 

 

 

 

 

 

 

pins are strap pins. For more information, see Table 16 on Page 20.

 

 

LxDATI3–0P

I

VDD_IO

Link Ports 3–0 Data 3–0 Receive LVDS P

 

 

LxDATI3–0N

I

VDD_IO

Link Ports 3–0 Data 3–0 Receive LVDS N

 

 

LxCLKINP

I/A

VDD_IO

Link Ports 3–0 Receive Clock LVDS P

 

 

LxCLKINN

I/A

VDD_IO

Link Ports 3–0 Receive Clock LVDS N

 

 

LxACKO

O

nc

Link Ports 3–0 Transmit Acknowledge. Using this signal, the receiver indicates to the

 

 

 

 

 

 

 

transmitter that it may continue the transmission.

 

 

 

 

I (pd_l)

VSS

Link Ports 3–0 Block Completion. When the reception is executed using DMA, this

 

 

LxBCMPI

 

 

 

 

 

 

 

signal indicates to the receiver that the transmitted block is completed.

 

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ; pd_l = internal pull-down 50 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

Table 12. Pin Definitions—Impedance Control, Drive Strength Control, and Regulator Enable

Signal

Type

Term

Description

CONTROLIMP0

I (pd)

na

Impedance Control. As shown in Table 13, the CONTROLIMP1–0 pins select between

CONTROLIMP1

I (pu)

na

normal driver mode and A/D driver mode. When using normal mode (recommended),

 

 

 

the output drive strength is set relative to maximum drive strength according to

 

 

 

Table 14. When using A/D mode, the resistance control operates in the analog mode,

 

 

 

where drive strength is continuously controlled to match a specific line impedance as

 

 

 

shown in Table 14.

DS2, 0

I (pu)

na

Digital Drive Strength Selection. Selected as shown in Table 14. For drive strength calcu-

DS1

I (pd)

 

lation, see Output Drive Currents on Page 36. The drive strength for some pins is preset,

 

 

 

not controlled by the DS2–0 pins. The pins that are always at drive strength 7 (100%)

 

 

 

include:

 

 

 

TDO,

 

and

 

The drive strength for the ACK pin is always

 

 

 

CPA,

DPA,

EMU,

RST_OUT.

 

 

 

x2 drive strength 7 (100%).

ENEDREG

I (pu)

VSS

Connect the ENEDREG pin to VSS. Connect the VDD_DRAM pins to a properly decoupled

 

 

 

DRAM power supply.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

Rev. C Page 18 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S Benchmark Speed Cycles General-Purpose Algorithm Benchmarks at 600 MHzClock FIR filter per real tap 83 nsDual Compute Blocks Data Alignment Buffer DABDual Integer ALU Ialu Interrupt Controller Program SequencerDSP Memory Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceMultiprocessor Interface DMA ControllerHost Interface Sdram ControllerDMA controller provides these additional features No Boot, Run from Memory Addresses Timer and GENERAL-PURPOSE I/OReset and Booting Link Ports LvdsPower Domains Filtering Reference Voltage and ClocksDevelopment Tools Evaluation KIT Additional InformationSclk Ratio Pin Definitions-Clocks and ResetSignal Type Term Description RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationSample the data instead of the TigerSHARC Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA MakesHdqm Pin Definitions-External Port Sdram ControllerLdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionCONTROLIMP1 Pin Definitions-Link PortsCONTROLIMP0 DS1DS2-0 Drive Output Pins Strength Impedance Pin Definitions-Power, Ground, and ReferenceDriver Mode Impedance Control SelectionPin Definitions-I/O Strap Pins Type at Signal ResetPin Rstin = Operating Conditions SclkvrefMaximum Duty Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage VIN Max VIN Min Cycle2Absolute Maximum Ratings Package InformationESD Sensitivity Package Brand InformationGeneral AC Timing Timing SpecificationsAC Asynchronous Signal Specifications Reference Clocks-Core Clock Cclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 DS2-0 Static Pins-Must Be ConstantStrap Pins Strap SYS 9Parameter Description Test Conditions Min Max Unit Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Environmental Conditions Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsL0DATI1N Sdcke SCLKRAT1L0ACKO L0DATI3NDS1 CONTROLIMP1 TDO FLAG3 DS2 Enedreg TCKID2 TDI TMR0E L1CLKINNPackage Ball Attach Type Solder Mask Opening Ball Pad Size Surface Mount DesignBGA Data for Use with Surface Mount Design Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Temperature Instruction On-Chip Package Model Range1 Rate2 Ordering GuideOperating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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