Analog Devices ADSP-TS201S External Port OFF-CHIP MEMORY/PERIPHERALS Interface, Internal Space

Page 6

ADSP-TS201S

INTERNAL SPACE

RESERVED

SOC REGISTERS (UREGS)

RESERVED

INTERNAL REGISTERS (UREGS)

RESERVED

INTERNAL MEMORY BLOCK 10

RESERVED

INTERNAL MEMORY BLOCK 8

RESERVED

INTERNAL MEMORY BLOCK 6

RESERVED

INTERNAL MEMORY BLOCK 4

RESERVED

INTERNAL MEMORY BLOCK 2

RESERVED

INTERNAL MEMORY BLOCK 0

0x03FFFFFF

0x001F03FF

0x001F0000

0x001E03FF

0x001E0000

0x0015FFFF

0x00140000

0x0011FFFF

0x00100000

0x000DFFFF

0x000C0000

0x0009FFFF

0x00080000

0x0005FFFF

0x00040000

0x0001FFFF

0x00000000

 

GLOBAL SPACE

 

HOST (MSH)

 

 

 

RESERVED

 

MSSD BANK 3 (MSSD3)

 

 

 

RESERVED

SPACE

MSSD BANK 2 (MSS D2)

 

 

 

MEMORY

RESERVED

MSSD BANK 1 (MSSD1)

 

 

 

EXTERNAL

RESERVED

MSSD BANK 0 (MSSD0)

 

 

 

 

BANK 1 (MS 1)

 

 

 

BANK 0 (MS 0)

 

 

SPACE

PROCESSOR ID 7

 

PROCESSOR ID 6

MEMORY

 

PROCESSOR ID 5

 

 

 

PROCESSOR ID 4

MULTIPROCESSOR

 

PROCESSOR ID 3

 

 

 

PROCESSOR ID 2

 

 

 

PROCESSOR ID 1

 

 

 

PROCESSOR ID 0

 

 

 

BROADCAST

 

 

 

RESERVED

 

 

 

INTERNAL MEMORY

 

 

Figure 3. ADSP-TS201S Memory Map

0xFFFFFFFF

0x80000000

0x74000000

0x70000000

0x64000000

0x60000000

0x54000000

0x50000000

0x44000000

0x40000000

0x38000000

0x30000000

0x2C000000

0x28000000

0x24000000

0x20000000

0x1C000000

0x18000000

0x14000000

0x10000000

0x0C000000

0x03FFFFFF

0x00000000

EACH IS A COPY

OF INTERNAL SPACE

33.6G bytes per second, enabling the core and I/O to access eight 32-bit data-words and four 32-bit instructions each cycle. The DSP’s flexible memory structure enables:

•DSP core and I/O accesses to different memory blocks in the same cycle

•DSP core access to three memory blocks in parallel—one instruction and two data accesses

•Programmable partitioning of program and data memory

•Program access of all memory as 32-, 64-, or 128-bit words—16-bit words with the DAB

EXTERNAL PORT

(OFF-CHIP MEMORY/PERIPHERALS INTERFACE)

The ADSP-TS201S processor’s external port provides the DSP’s interface to off-chip memory and peripherals. The 4G word address space is included in the DSP’s unified address space.

The separate on-chip buses—four 128-bit data buses and four 32-bit address buses—are multiplexed at the SOC interface and transferred to the external port over the SOC bus to create an external system bus transaction. The external system bus pro- vides a single 64-bit data bus and a single 32-bit address bus. The external port supports data transfer rates of 1G byte per second over the external bus.

The external bus can be configured for 32-bit or 64-bit, little- endian operations. When the system bus is configured for 64-bit operations, the lower 32 bits of the external data bus connect to even addresses, and the upper 32 bits connect to odd addresses.

The external port supports pipelined, slow, and SDRAM proto- cols. Addressing of external memory devices and memory- mapped peripherals is facilitated by on-chip decoding of high order address lines to generate memory bank select signals.

Rev. C Page 6 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S Benchmark Speed Cycles General-Purpose Algorithm Benchmarks at 600 MHzClock FIR filter per real tap 83 nsDual Compute Blocks Data Alignment Buffer DABDual Integer ALU Ialu Interrupt Controller Program SequencerDSP Memory Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceMultiprocessor Interface DMA ControllerHost Interface Sdram ControllerDMA controller provides these additional features No Boot, Run from Memory Addresses Timer and GENERAL-PURPOSE I/OReset and Booting Link Ports LvdsPower Domains Filtering Reference Voltage and ClocksDevelopment Tools Evaluation KIT Additional InformationSclk Ratio Pin Definitions-Clocks and ResetSignal Type Term Description RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationSample the data instead of the TigerSHARC Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA MakesHdqm Pin Definitions-External Port Sdram ControllerLdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionCONTROLIMP1 Pin Definitions-Link PortsCONTROLIMP0 DS1DS2-0 Drive Output Pins Strength Impedance Pin Definitions-Power, Ground, and ReferenceDriver Mode Impedance Control SelectionPin Definitions-I/O Strap Pins Type at Signal ResetPin Rstin = Operating Conditions SclkvrefMaximum Duty Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage VIN Max VIN Min Cycle2Absolute Maximum Ratings Package InformationESD Sensitivity Package Brand InformationGeneral AC Timing Timing SpecificationsAC Asynchronous Signal Specifications Reference Clocks-Core Clock Cclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 DS2-0 Static Pins-Must Be ConstantStrap Pins Strap SYS 9Parameter Description Test Conditions Min Max Unit Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Environmental Conditions Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsL0DATI1N Sdcke SCLKRAT1L0ACKO L0DATI3NDS1 CONTROLIMP1 TDO FLAG3 DS2 Enedreg TCKID2 TDI TMR0E L1CLKINNPackage Ball Attach Type Solder Mask Opening Ball Pad Size Surface Mount DesignBGA Data for Use with Surface Mount Design Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Temperature Instruction On-Chip Package Model Range1 Rate2 Ordering GuideOperating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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