Analog Devices ADSP-TS201S Sdcke SCLKRAT1, L0ACKO, L0DATI1N, L0DATI3N, L0DATI1P, L0DATI3P, DS0

Page 43

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADSP-TS201S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ball No.

Signal Name

Ball No.

Signal Name

Ball No.

Signal Name

Ball No.

Signal Name

 

J1

 

 

 

 

 

K1

 

SDA10

L1

 

 

 

 

 

 

M1

 

 

 

 

 

 

 

RAS

SDWE

BR3

 

J2

 

 

 

 

K2

 

SDCKE

L2

 

 

 

 

 

M2

 

SCLKRAT1

 

CAS

 

 

BR0

 

 

J3

 

VSS

K3

 

LDQM

L3

 

 

 

 

 

M3

 

 

 

 

 

 

 

 

 

BR1

BR5

 

J4

 

VREF

K4

 

HDQM

L4

 

 

 

 

 

M4

 

 

 

 

 

 

 

 

 

BR2

BR6

 

J5

 

VSS

K5

 

VDD_IO

L5

 

 

VDD_IO

M5

 

VDD_IO

 

J6

 

VDD

K6

 

VDD

L6

 

 

VDD

M6

 

VDD

 

J7

 

VDD

K7

 

VDD

L7

 

 

VDD

M7

 

VDD

 

J8

 

VSS

K8

 

VSS

L8

 

 

VSS

M8

 

VSS

 

J9

 

VSS

K9

 

VSS

L9

 

 

VSS

M9

 

VSS

 

J10

 

VSS

K10

 

VSS

L10

 

 

VSS

M10

 

VSS

 

J11

 

VSS

K11

 

VSS

L11

 

 

VSS

M11

 

VSS

 

J12

 

VSS

K12

 

VSS

L12

 

 

VSS

M12

 

VSS

 

J13

 

VSS

K13

 

VSS

L13

 

 

VSS

M13

 

VSS

 

J14

 

VSS

K14

 

VSS

L14

 

 

VSS

M14

 

VSS

 

J15

 

VSS

K15

 

VSS

L15

 

 

VSS

M15

 

VSS

 

J16

 

VSS

K16

 

VSS

L16

 

 

VSS

M16

 

VSS

 

J17

 

VSS

K17

 

VSS

L17

 

 

VSS

M17

 

VSS

 

J18

 

VDD

K18

 

VDD_DRAM

L18

 

 

VDD_DRAM

M18

 

VDD

 

J19

 

VDD

K19

 

VDD_DRAM

L19

 

 

VDD_DRAM

M19

 

VDD

 

J20

 

VSS

K20

 

VDD_IO

L20

 

 

VDD_IO

M20

 

VDD_IO

 

J21

 

L0ACKO

K21

L0DATI1_N

L21

L0DATI3_N

M21

VSS

 

J22

 

L0BCMPI

 

K22

L0DATI1_P

L22

 

 

L0DATI3_P

M22

 

VSS

 

J23

 

L0DATI0_N

K23

L0CLKINN

L23

L0DATI2_N

M23

L0DATO3_N

 

J24

 

L0DATI0_P

K24

L0CLKINP

L24

L0DATI2_P

M24

L0DATO3_P

 

N1

 

ID0

P1

 

SCLK

R1

 

 

VSS

T1

 

 

 

 

 

 

 

 

 

 

RST_IN

 

N2

 

VSS

P2

 

SCLK_VREF

R2

NC (SCLK)1

T2

 

SCLKRAT2

 

N3

 

VDD_A

P3

 

VSS

R3

 

 

NC (SCLK_VREF)1

T3

 

 

 

 

 

 

 

 

BR4

 

N4

 

VDD_A

P4

 

 

 

R4

 

 

 

 

 

T4

 

DS0

 

 

BM

 

 

BR7

 

 

N5

 

VDD_IO

P5

 

VDD_IO

R5

 

 

VDD_IO

T5

 

VSS

 

N6

 

VDD

P6

 

VDD

R6

 

 

VDD

T6

 

VDD

 

N7

 

VDD

P7

 

VDD

R7

 

 

VDD

T7

 

VDD

 

N8

 

VSS

P8

 

VSS

R8

 

 

VSS

T8

 

VSS

 

N9

 

VSS

P9

 

VSS

R9

 

 

VSS

T9

 

VSS

 

N10

 

VSS

P10

 

VSS

R10

 

 

VSS

T10

 

VSS

 

N11

 

VSS

P11

 

VSS

R11

 

 

VSS

T11

 

VSS

 

N12

 

VSS

P12

 

VSS

R12

 

 

VSS

T12

 

VSS

 

N13

 

VSS

P13

 

VSS

R13

 

 

VSS

T13

 

VSS

 

N14

 

VSS

P14

 

VSS

R14

 

 

VSS

T14

 

VSS

 

N15

 

VSS

P15

 

VSS

R15

 

 

VSS

T15

 

VSS

 

N16

 

VSS

P16

 

VSS

R16

 

 

VSS

T16

 

VSS

 

N17

 

VSS

P17

 

VSS

R17

 

 

VSS

T17

 

VSS

 

N18

 

VDD

P18

 

VDD_DRAM

R18

 

 

VDD_DRAM

T18

 

VDD

 

N19

 

VDD

P19

 

VDD_DRAM

R19

 

 

VDD_DRAM

T19

 

VDD

 

N20

 

VDD_IO

P20

 

VDD_IO

R20

 

 

VDD_IO

T20

 

VSS

 

N21

 

L0DATO2_N

P21

L0DATO1_N

R21

NC

T21

L1DATI0_N

 

N22

 

L0DATO2_P

P22

L0DATO1_P

R22

VSS

T22

 

L1DATI0_P

 

N23

 

L0CLKON

P23

L0DATO0_N

R23

 

L0BCMPO

 

T23

L1ACKO

 

N24

 

L0CLKOP

P24

L0DATO0_P

R24

L0ACKI

T24

 

 

 

 

 

L1BCMPI

Rev. C Page 43 of 48 December 2006

Image 43
Contents ADSP-TS201S ADSP-TS201S FIR filter per real tap 83 ns General-Purpose Algorithm Benchmarks at 600 MHzClock Benchmark Speed CyclesData Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu Flexible Instruction Set Program SequencerDSP Memory Interrupt ControllerInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceSdram Controller DMA ControllerHost Interface Multiprocessor InterfaceDMA controller provides these additional features Link Ports Lvds Timer and GENERAL-PURPOSE I/OReset and Booting No Boot, Run from Memory AddressesFiltering Reference Voltage and Clocks Power DomainsDevelopment Tools Additional Information Evaluation KITRatio Pin Definitions-Clocks and ResetSignal Type Term Description Sclk RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeMakes Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA Sample the data instead of the TigerSHARCSDA10 Pin Definitions-External Port Sdram ControllerLdqm HdqmPin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerDS1 Pin Definitions-Link PortsCONTROLIMP0 CONTROLIMP1Impedance Control Selection Pin Definitions-Power, Ground, and ReferenceDriver Mode DS2-0 Drive Output Pins Strength ImpedanceType at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Sclkvref Operating ConditionsVIN Max VIN Min Cycle2 Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage Maximum DutyPackage Brand Information Package InformationESD Sensitivity Absolute Maximum RatingsReference Clocks-Core Clock Cclk Cycle Time Timing SpecificationsAC Asynchronous Signal Specifications General AC TimingParameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Sclkrat = 5⋅, 7⋅ Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap SYS 9 DS2-0 Static Pins-Must Be ConstantStrap Pins Jtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0VOD Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Parameter Condition Typical Unit Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Environmental ConditionsBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0DATI3N Sdcke SCLKRAT1L0ACKO L0DATI1NL1CLKINN DS2 Enedreg TCKID2 TDI TMR0E DS1 CONTROLIMP1 TDO FLAG3Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Surface Mount DesignBGA Data for Use with Surface Mount Design Package Ball Attach Type Solder Mask Opening Ball Pad SizeOrdering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December