Analog Devices ADSP-TS201S Ball 25 mm × 25 mm Bgaed Ball Assignments, Ball No Signal Name

Page 42

ADSP-TS201S

Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments

Ball No.

 

Signal Name

Ball No.

 

Signal Name

Ball No.

 

Signal Name

Ball No.

 

Signal Name

A1

 

VSS

B1

 

DATA53

C1

 

VSS

D1

 

DATA55

A2

 

DATA51

B2

 

VSS

C2

 

VSS

D2

 

DATA56

A3

 

VSS

B3

 

VSS

C3

 

VSS

D3

 

DATA54

A4

 

DATA49

B4

 

DATA50

C4

 

DATA52

D4

VSS

A5

 

DATA43

B5

 

DATA44

C5

 

DATA47

D5

DATA48

A6

 

DATA41

B6

 

DATA42

C6

 

DATA45

D6

DATA46

A7

 

DATA37

B7

 

DATA38

C7

 

DATA39

D7

DATA40

A8

 

DATA33

B8

 

DATA34

C8

 

DATA35

D8

DATA36

A9

 

DATA29

B9

 

DATA30

C9

 

DATA31

D9

DATA32

A10

 

DATA25

B10

 

DATA26

C10

DATA27

D10

DATA28

A11

 

DATA23

B11

 

DATA24

C11

DATA21

D11

DATA22

A12

 

DATA19

B12

 

DATA20

C12

DATA17

D12

DATA18

A13

 

DATA15

B13

 

DATA16

C13

 

VSS

D13

 

VSS

A14

 

DATA11

B14

 

DATA12

C14

DATA13

D14

DATA14

A15

 

DATA9

B15

DATA10

C15

DATA7

D15

DATA8

A16

 

DATA5

B16

DATA6

C16

DATA3

D16

DATA4

A17

 

DATA1

B17

DATA2

C17

ACK

D17

 

DATA0

A18

 

 

 

B18

 

 

 

 

C18

 

 

 

 

 

 

D18

 

 

 

 

 

WRL

WRH

RD

BRST

A19

 

ADDR30

B19

 

ADDR31

C19

 

ADDR26

D19

ADDR27

A20

 

ADDR28

B20

 

ADDR29

C20

 

ADDR24

D20

ADDR25

A21

 

ADDR22

B21

 

ADDR23

C21

 

ADDR20

D21

VSS

A22

 

VSS

B22

 

VSS

C22

 

VSS

D22

 

ADDR19

A23

 

ADDR21

B23

 

VSS

C23

 

VDD_IO

D23

 

ADDR17

A24

 

VSS

B24

 

ADDR18

C24

VDD_IO

D24

 

ADDR16

E1

 

DATA61

F1

 

DATA63

G1

 

 

 

 

 

 

H1

 

VSS

 

 

MSSD1

 

E2

 

DATA62

F2

 

 

 

G2

 

VSS

H2

 

 

 

 

MS1

 

 

MSH

E3

 

DATA57

F3

 

DATA59

G3

 

 

 

 

H3

 

 

 

 

 

MS0

 

MSSD3

E4

 

DATA58

F4

 

DATA60

G4

 

 

 

H4

 

SCLKRAT0

 

 

BMS

 

E5

 

VSS

F5

 

VDD_IO

G5

 

VSS

H5

 

VDD_IO

E6

 

VDD_IO

F6

 

VDD

G6

 

VDD

H6

 

VDD

E7

 

VSS

F7

 

VDD

G7

 

VDD

H7

 

VDD

E8

 

VDD_IO

F8

 

VDD

G8

 

VDD

H8

 

VSS

E9

 

VSS

F9

 

VDD

G9

 

VDD

H9

 

VSS

E10

 

VDD_IO

F10

 

VDD

G10

 

VDD

H10

 

VSS

E11

 

VDD_IO

F11

 

VDD_DRAM

G11

 

VDD_DRAM

H11

 

VSS

E12

 

VDD_IO

F12

 

VDD_DRAM

G12

 

VDD_DRAM

H12

 

VSS

E13

 

VDD_IO

F13

 

VDD

G13

 

VDD

H13

 

VSS

E14

 

VDD_IO

F14

 

VDD

G14

 

VDD

H14

 

VSS

E15

 

VDD_IO

F15

 

VDD_DRAM

G15

 

VDD_DRAM

H15

 

VSS

E16

 

VSS

F16

 

VDD_DRAM

G16

 

VDD_DRAM

H16

 

VSS

E17

 

VDD_IO

F17

 

VDD

G17

 

VDD

H17

 

VSS

E18

 

VSS

F18

 

VDD

G18

 

VDD

H18

 

VDD

E19

 

VDD_IO

F19

 

VDD

G19

 

VDD

H19

 

VDD

E20

 

VSS

F20

 

VDD_IO

G20

 

VDD_IO

H20

 

VDD_IO

E21

 

ADDR15

F21

 

ADDR13

G21

 

ADDR7

H21

 

ADDR3

E22

 

ADDR14

F22

 

ADDR12

G22

 

ADDR6

H22

 

ADDR2

E23

 

ADDR11

F23

ADDR9

G23

ADDR5

H23

ADDR1

E24

 

ADDR10

F24

ADDR8

G24

ADDR4

H24

ADDR0

Rev. C Page 42 of 48 December 2006

Image 42
Contents ADSP-TS201S ADSP-TS201S Benchmark Speed Cycles General-Purpose Algorithm Benchmarks at 600 MHzClock FIR filter per real tap 83 nsDual Compute Blocks Data Alignment Buffer DABDual Integer ALU Ialu Interrupt Controller Program SequencerDSP Memory Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceMultiprocessor Interface DMA ControllerHost Interface Sdram ControllerDMA controller provides these additional features No Boot, Run from Memory Addresses Timer and GENERAL-PURPOSE I/OReset and Booting Link Ports LvdsPower Domains Filtering Reference Voltage and ClocksDevelopment Tools Evaluation KIT Additional InformationSclk Ratio Pin Definitions-Clocks and ResetSignal Type Term Description RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationSample the data instead of the TigerSHARC Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA MakesHdqm Pin Definitions-External Port Sdram ControllerLdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionCONTROLIMP1 Pin Definitions-Link PortsCONTROLIMP0 DS1DS2-0 Drive Output Pins Strength Impedance Pin Definitions-Power, Ground, and ReferenceDriver Mode Impedance Control SelectionPin Definitions-I/O Strap Pins Type at Signal ResetPin Rstin = Operating Conditions SclkvrefMaximum Duty Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage VIN Max VIN Min Cycle2Absolute Maximum Ratings Package InformationESD Sensitivity Package Brand InformationGeneral AC Timing Timing SpecificationsAC Asynchronous Signal Specifications Reference Clocks-Core Clock Cclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 DS2-0 Static Pins-Must Be ConstantStrap Pins Strap SYS 9Parameter Description Test Conditions Min Max Unit Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Environmental Conditions Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsL0DATI1N Sdcke SCLKRAT1L0ACKO L0DATI3NDS1 CONTROLIMP1 TDO FLAG3 DS2 Enedreg TCKID2 TDI TMR0E L1CLKINNPackage Ball Attach Type Solder Mask Opening Ball Pad Size Surface Mount DesignBGA Data for Use with Surface Mount Design Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Temperature Instruction On-Chip Package Model Range1 Rate2 Ordering GuideOperating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December