Analog Devices ADSP-TS201S specifications Pin Definitions-Clocks and Reset, Sclk Ratio

Page 12

ADSP-TS201S

PIN FUNCTION DESCRIPTIONS

While most of the ADSP-TS201S processor’s input pins are nor- mally synchronous—tied to a specific clock—a few are asynchronous. For these asynchronous signals, an on-chip syn- chronization circuit prevents metastability problems. Use the ac specification for asynchronous signals when the system design requires predictable, cycle-by-cycle behavior for these signals.

Table 3. Pin Definitions—Clocks and Reset

The output pins can be three-stated during normal operation. The DSP three-states all output pins during reset, allowing these pins to get to their internal pull-up or pull-down state. Some pins have an internal pull-up or pull-down resistor (±30% toler- ance) that maintains a known value during transitions between different drivers.

 

Signal

Type

Term

Description

 

SCLKRAT2–0

I (pd)

na

Core Clock Ratio. The DSP’s core clock (CCLK) rate = n × SCLK, where n is user-

 

 

 

 

 

 

 

programmable using the SCLKRATx pins to the values shown in Table 4. These pins

 

 

 

 

 

 

 

may change only during reset; connect these pins to VDD_IO or VSS. All reset specifica-

 

 

 

 

 

 

 

tions in Table 25, Table 26, and Table 27 must be satisfied. The core clock rate (CCLK)

 

 

 

 

 

 

 

is the instruction cycle rate.

SCLK

I

na

System Clock Input. The DSP’s system input clock for cluster bus. The core clock rate

 

 

 

 

 

 

 

is user-programmable using the SCLKRATx pins. For more information, see Clock

 

 

 

 

 

 

 

Domains on Page 9.

 

 

 

 

 

I/A

na

Reset. Sets the DSP to a known state and causes program to be in idle state.

 

 

RST_IN

RST_IN

 

 

 

 

 

 

 

must be asserted a specified time according to the type of reset operation. For details,

 

 

 

 

 

 

 

see Reset and Booting on Page 9, Table 25 on Page 26, and Figure 13 on Page 26.

 

 

 

 

O

na

Reset Output. Indicates that the DSP reset is complete. Connect to

 

 

RST_OUT

POR_IN.

 

 

 

I/A

na

Power-On Reset for internal DRAM. Connect to

 

 

 

POR_IN

RST_OUT.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

Table 4. SCLK Ratio

SCLKRAT2–0

Ratio

000

(default)

4

001

 

5

010

 

6

011

 

7

100

 

8

101

 

10

110

 

12

111

 

Reserved

Rev. C Page 12 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S General-Purpose Algorithm Benchmarks at 600 MHz ClockBenchmark Speed Cycles FIR filter per real tap 83 nsDual Compute Blocks Data Alignment Buffer DABDual Integer ALU Ialu Program Sequencer DSP MemoryInterrupt Controller Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceDMA Controller Host InterfaceMultiprocessor Interface Sdram ControllerDMA controller provides these additional features Timer and GENERAL-PURPOSE I/O Reset and BootingNo Boot, Run from Memory Addresses Link Ports LvdsPower Domains Filtering Reference Voltage and ClocksDevelopment Tools Evaluation KIT Additional InformationPin Definitions-Clocks and Reset Signal Type Term DescriptionSclk Ratio RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationPin Definitions-External Port DMA/Flyby DSP performs DMA transfers according to the DMASample the data instead of the TigerSHARC MakesPin Definitions-External Port Sdram Controller LdqmHdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionPin Definitions-Link Ports CONTROLIMP0CONTROLIMP1 DS1Pin Definitions-Power, Ground, and Reference Driver ModeDS2-0 Drive Output Pins Strength Impedance Impedance Control SelectionPin Definitions-I/O Strap Pins Type at Signal ResetPin Rstin = Operating Conditions SclkvrefElectrical Characteristics Maximum Duty Cycle for Input Transient VoltageMaximum Duty VIN Max VIN Min Cycle2Package Information ESD SensitivityAbsolute Maximum Ratings Package Brand InformationTiming Specifications AC Asynchronous Signal SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle TimeReference Clocks-System Clock Sclk Cycle Time Reference Clocks-JTAG Test Clock TCK Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxDS2-0 Static Pins-Must Be Constant Strap PinsJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9Link Port Lvds Transmit Electrical Characteristics Link Port Lvds Receive Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Thermal Characteristics Thermal Characteristics for 25 mm × 25 mm PackageEnvironmental Conditions Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsSdcke SCLKRAT1 L0ACKOL0DATI1N L0DATI3NDS2 Enedreg TCK ID2 TDI TMR0EDS1 CONTROLIMP1 TDO FLAG3 L1CLKINNSurface Mount Design BGA Data for Use with Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Temperature Instruction On-Chip Package Model Range1 Rate2 Ordering GuideOperating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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