Analog Devices ADSP-TS201S specifications Pin Definitions-External Port Arbitration, Signal Type

Page 14

ADSP-TS201S

Table 6. Pin Definitions—External Port Arbitration

 

Signal

 

Type

Term

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BR7–0

 

I/O

VDD_IO

 

Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

arbitrate for bus mastership. Each DSP drives its own

BRx

 

 

line (corresponding to the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSPs, set the unused

 

 

 

 

pins high (VDD_IO).

 

 

 

 

 

 

 

 

 

 

 

 

 

BRx

 

ID2–0

 

I (pd)

na

 

Multiprocessor ID. Indicates the DSP’s ID, from which the DSP determines its order in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a multiprocessor system. These pins also indicate to the DSP which bus request

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(BR0–BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2,

 

 

 

 

 

 

 

 

 

 

 

 

 

011 =

BR3,

100 =

BR4,

101 =

 

BR5,

110 =

BR6,

or 111 =

BR7.

ID2–0 must have a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

constant value during system operation and can change during reset only.

 

 

 

 

 

 

 

 

 

O

na

 

Bus Master. The current bus master DSP asserts

 

 

 

 

For debugging only. At reset this

 

BM

 

BM.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is a strap pin. For more information, see Table 16 on Page 20.

 

 

 

 

 

 

 

 

I

epu

 

 

Back Off. A deadlock situation can occur when the host and a DSP try to read from

BOFF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

each other’s bus at the same time. When deadlock occurs, the host can assert

BOFF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

to force the DSP to relinquish the bus before completing its outstanding transaction.

 

 

 

 

 

 

 

O/T

na

 

 

Bus Lock Indication. Provides an indication that the current bus master has locked the

 

BUSLOCK

 

 

 

 

 

 

 

 

 

 

 

(pu_0)

 

 

 

bus. At reset, this is a strap pin. For more information, see Table 16 on Page 20.

 

 

 

 

 

 

 

I

epu

 

 

Host Bus Request. A host must assert

 

 

 

to request control of the DSP’s external bus.

HBR

 

HBR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When

HBR

is asserted in a multiprocessing system, the bus master relinquishes the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bus and asserts

HBG

once the outstanding transaction is finished.

 

 

 

 

 

 

I/O/T

epu2

 

 

Host Bus Grant. Acknowledges

 

and indicates that the host can take control of

 

HBG

 

HBR

 

 

 

 

 

 

 

 

 

 

(pu_0)

 

 

 

the external bus. When relinquishing the bus, the master DSP three-states the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDR31–0, DATA63–0,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSH,

MSSD3–0,

MS1–0,

RD,

WRL,

WRH,

BMS,

BRST,

IORD,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOWR,

 

IOEN,

 

RAS,

 

CAS,

 

SDWE,

SDA10, SDCKE, LDQM, and HDQM pins, and the DSP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

puts the SDRAM in self-refresh mode. The DSP asserts

HBG

until the host deasserts

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HBR.

In multiprocessor systems, the current bus master DSP drives

HBG,

and all slave

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSPs monitor it.

 

 

 

 

 

I/O/OD

epu2

 

 

Core Priority Access. Asserted while the DSP’s core accesses external memory. This

 

CPA

 

 

 

 

 

 

 

 

 

 

 

 

(pu_od_0)

 

 

 

pin enables a slave DSP to interrupt a master DSP’s background DMA transfers and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

gain control of the external bus for core-initiated transactions.

 

is an open drain

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

output, connected to all DSPs in the system. If not required in the system, leave

CPA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

unconnected (external pull-ups will be required for DSP ID = 1 through ID = 7).

 

 

 

 

I/O/OD

epu2

 

 

DMA Priority Access. Asserted while a high priority DSP DMA channel accesses

 

DPA

 

 

 

 

 

 

 

 

 

 

 

 

(pu_od_0)

 

 

 

external memory. This pin enables a high priority DMA channel on a slave DSP to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

interrupt transfers of a normal priority DMA channel on a master DSP and gain control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

of the external bus for DMA-initiated transactions.

 

is an open drain output,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DPA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

connected to all DSPs in the system. If not required in the system, leave

DPA

uncon-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

nected (external pull-ups will be required for DSP ID = 1 through ID = 7).

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

1The BRx pin matching the ID2–0 input selection for the processor should be left nc if unused. For example, the processor with ID = 000 has BR0 = nc and BR7–1 = VDD_IO.

2 This external pull-up resistor may be omitted for the ID = 000 TigerSHARC processor.

Rev. C Page 14 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S Benchmark Speed Cycles General-Purpose Algorithm Benchmarks at 600 MHzClock FIR filter per real tap 83 nsDual Integer ALU Ialu Dual Compute BlocksData Alignment Buffer DAB Interrupt Controller Program SequencerDSP Memory Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceMultiprocessor Interface DMA ControllerHost Interface Sdram ControllerDMA controller provides these additional features No Boot, Run from Memory Addresses Timer and GENERAL-PURPOSE I/OReset and Booting Link Ports LvdsDevelopment Tools Power DomainsFiltering Reference Voltage and Clocks Evaluation KIT Additional InformationSclk Ratio Pin Definitions-Clocks and ResetSignal Type Term Description RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationSample the data instead of the TigerSHARC Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA MakesHdqm Pin Definitions-External Port Sdram ControllerLdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionCONTROLIMP1 Pin Definitions-Link PortsCONTROLIMP0 DS1DS2-0 Drive Output Pins Strength Impedance Pin Definitions-Power, Ground, and ReferenceDriver Mode Impedance Control SelectionPin Rstin = Pin Definitions-I/O Strap PinsType at Signal Reset Operating Conditions SclkvrefMaximum Duty Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage VIN Max VIN Min Cycle2Absolute Maximum Ratings Package InformationESD Sensitivity Package Brand InformationGeneral AC Timing Timing SpecificationsAC Asynchronous Signal Specifications Reference Clocks-Core Clock Cclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 DS2-0 Static Pins-Must Be ConstantStrap Pins Strap SYS 9Parameter Description Test Conditions Min Max Unit Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Environmental Conditions Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsL0DATI1N Sdcke SCLKRAT1L0ACKO L0DATI3NDS1 CONTROLIMP1 TDO FLAG3 DS2 Enedreg TCKID2 TDI TMR0E L1CLKINNPackage Ball Attach Type Solder Mask Opening Ball Pad Size Surface Mount DesignBGA Data for Use with Surface Mount Design Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Operating Voltage Option Description Temperature Instruction On-Chip Package Model Range1 Rate2Ordering Guide Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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