Analog Devices ADSP-TS201S Electrical Characteristics, Maximum Duty, VIN Max VIN Min Cycle2

Page 22

ADSP-TS201S

Table 18. Maximum Duty Cycle for Input Transient Voltage

 

 

Maximum Duty

VIN Max (V)1

VIN Min (V)1

Cycle2

+3.63

–0.33

100%

+3.64

–0.34

90%

+3.70

–0.40

50%

+3.78

–0.48

30%

+3.86

–0.56

17%

+3.93

–0.63

10%

1The individual values cannot be combined for analysis of a single instance of overshoot or undershoot. The worst case observed value must fall within one of the voltages specified and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle.

2Duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. This is equivalent to the measured duration of a single instance of overshoot or undershoot as a percentage of the period of occurrence. The practical worst case for period of occurrence for either overshoot or undershoot is 2 × tSCLK.

ELECTRICAL CHARACTERISTICS

Parameter

Description

Test Conditions

Min

Max

Unit

 

 

 

 

 

 

VOH

High Level Output Voltage1

@VDD_IO = Min, IOH = –2 mA

2.18

 

V

VOL

Low Level Output Voltage1

@VDD_IO = Min, IOL = 4 mA

 

0.4

V

IIH

High Level Input Current

@VDD_IO = Max, VIN = VIH Max

 

20

μA

IIH_PU

High Level Input Current

@VDD_IO = Max, VIN = VIH Max

 

20

μA

IIH_PD

High Level Input Current

@VDD_IO = Max, VIN = VDD_IO Max

0.3

0.76

mA

IIH_PD_L

High Level Input Current

@VDD_IO = Max, VIN = VIH Max

30

76

μA

IIL

Low Level Input Current

@VDD_IO = Max, VIN = 0 V

 

20

μA

IIL_PU

Low Level Input Current

@VDD_IO = Max, VIN = 0 V

0.3

0.76

mA

IIL_PU_AD

Low Level Input Current

@VDD_IO = Max, VIN = 0 V

30

100

μA

IOZH

Three-State Leakage Current High

@VDD_IO = Max, VIN = VIH Max

 

50

μA

IOZH_PD

Three-State Leakage Current High

@VDD_IO = Max, VIN = VDD_IO Max

0.3

0.76

mA

IOZL

Three-State Leakage Current Low

@VDD_IO = Max, VIN = 0 V

 

20

μA

IOZL_PU

Three-State Leakage Current Low

@VDD_IO = Max, VIN = 0 V

0.3

0.76

mA

IOZL_PU_AD

Three-State Leakage Current Low

@VDD_IO = Max, VIN = 0 V

30

100

μA

IOZL_OD

Three-State Leakage Current Low

@VDD_IO = Max, VIN = 0 V

4

7.6

mA

CIN

Input Capacitance2, 3

@fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V

 

3

pF

Parameter name suffix conventions: no suffix = applies to pins without pull-up or pull-down resistors, _PD = applies to pin types (pd) or (pd_0), _PU = applies to pin types (pu) or (pu_0), _PU_AD = applies to pin types (pu_ad), _OD = applies to pin types OD, _PD_L = applies to pin types (pd_l)

1Applies to output and bidirectional pins.

2 Applies to all signals.

3 Guaranteed but not tested.

Rev. C Page 22 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S Benchmark Speed Cycles General-Purpose Algorithm Benchmarks at 600 MHzClock FIR filter per real tap 83 nsData Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu Interrupt Controller Program SequencerDSP Memory Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceMultiprocessor Interface DMA ControllerHost Interface Sdram ControllerDMA controller provides these additional features No Boot, Run from Memory Addresses Timer and GENERAL-PURPOSE I/OReset and Booting Link Ports LvdsFiltering Reference Voltage and Clocks Power DomainsDevelopment Tools Evaluation KIT Additional InformationSclk Ratio Pin Definitions-Clocks and ResetSignal Type Term Description RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationSample the data instead of the TigerSHARC Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA MakesHdqm Pin Definitions-External Port Sdram ControllerLdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionCONTROLIMP1 Pin Definitions-Link PortsCONTROLIMP0 DS1DS2-0 Drive Output Pins Strength Impedance Pin Definitions-Power, Ground, and ReferenceDriver Mode Impedance Control SelectionType at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Operating Conditions SclkvrefMaximum Duty Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage VIN Max VIN Min Cycle2Absolute Maximum Ratings Package InformationESD Sensitivity Package Brand InformationGeneral AC Timing Timing SpecificationsAC Asynchronous Signal Specifications Reference Clocks-Core Clock Cclk Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 DS2-0 Static Pins-Must Be ConstantStrap Pins Strap SYS 9Parameter Description Test Conditions Min Max Unit Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Environmental Conditions Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsL0DATI1N Sdcke SCLKRAT1L0ACKO L0DATI3NDS1 CONTROLIMP1 TDO FLAG3 DS2 Enedreg TCKID2 TDI TMR0E L1CLKINNPackage Ball Attach Type Solder Mask Opening Ball Pad Size Surface Mount DesignBGA Data for Use with Surface Mount Design Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Ordering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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