Analog Devices ADSP-TS201S Pin Definitions-External Port Sdram Controller, Ldqm, Hdqm, SDA10

Page 16

ADSP-TS201S

Table 8. Pin Definitions—External Port SDRAM Controller

 

Signal

 

Type

Term

Description

 

 

 

 

 

 

I/O/T

nc

Memory Select SDRAM.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

is asserted whenever the

 

MSSD3–0

MSSD0,

MSSD1,

MSSD2,

MSSD3

 

 

 

 

 

 

(pu_0)

 

DSP accesses SDRAM memory space.

MSSD3–0

 

are decoded memory address pins

 

 

 

 

 

 

 

 

that are asserted whenever the DSP issues an SDRAM command cycle (access to

 

 

 

 

 

 

 

 

ADDR31:30 = 0b01—except reserved spaces shown in Figure 3 on Page 6). In a multi-

 

 

 

 

 

 

 

 

processor system, the master DSP drives

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSSD3–0.

 

 

 

 

 

 

I/O/T

nc

Row Address Select. When sampled low,

 

 

indicates that a row address is valid in

 

RAS

RAS

 

 

 

 

 

 

(pu_0)

 

a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation

 

 

 

 

 

 

 

 

to execute according to SDRAM specification.

 

 

 

 

 

I/O/T

nc

Column Address Select. When sampled low,

 

 

 

 

indicates that a column address is

CAS

CAS

 

 

 

 

 

 

(pu_0)

 

valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of

 

 

 

 

 

 

 

 

operation to execute according to the SDRAM specification.

 

LDQM

 

O/T

nc

Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ

 

 

 

 

 

 

(pu_0)

 

buffers. LDQM is valid on SDRAM transactions when

 

 

 

is asserted, and inactive on

 

 

 

 

 

 

CAS

 

 

 

 

 

 

 

 

read transactions. On write transactions, LDQM is active when accessing an odd

 

 

 

 

 

 

 

 

address word on a 64-bit memory bus to disable the write of the low word.

HDQM

 

O/T

nc

High Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ

 

 

 

 

 

 

(pu_0)

 

buffers. HDQM is valid on SDRAM transactions when

 

is asserted, and inactive on

 

 

 

 

 

 

CAS

 

 

 

 

 

 

 

 

read transactions. On write transactions, HDQM is active when accessing an even

 

 

 

 

 

 

 

 

address in word accesses or when memory is configured for a 32-bit bus to disable

 

 

 

 

 

 

 

 

the write of the high word.

 

SDA10

 

O/T

nc

SDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while

 

 

 

 

 

 

(pu_0)

 

the DSP executes non-SDRAM transactions.

SDCKE

 

I/O/T

nc

SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend

 

 

 

 

 

 

(pu_m/

 

modes. A slave DSP in a multiprocessor system does not have the pull-up or pull-

 

 

 

 

 

 

pd_m)

 

down. A master DSP (or ID = 0 in a single processor system) has a pull-up before

 

 

 

 

 

 

 

 

granting the bus to the host, except when the SDRAM is put in self refresh mode. In

 

 

 

 

 

 

 

 

self refresh mode, the master has a pull-down before granting the bus to the host.

 

 

 

 

I/O/T

nc

SDRAM Write Enable. When sampled low while

 

 

 

 

is active,

 

 

 

indicates an

SDWE

CAS

SDWE

 

 

 

 

 

 

(pu_0)

 

SDRAM write access. When sampled high while

CAS

is active,

SDWE

indicates an

 

 

 

 

 

 

 

 

SDRAM read access. In other SDRAM accesses,

SDWE

defines the type of operation to

 

 

 

 

 

 

 

 

execute according to SDRAM specification.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approx- imately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

Rev. C Page 16 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S General-Purpose Algorithm Benchmarks at 600 MHz ClockBenchmark Speed Cycles FIR filter per real tap 83 nsData Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu Program Sequencer DSP MemoryInterrupt Controller Flexible Instruction SetExternal Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal SpaceDMA Controller Host InterfaceMultiprocessor Interface Sdram ControllerDMA controller provides these additional features Timer and GENERAL-PURPOSE I/O Reset and BootingNo Boot, Run from Memory Addresses Link Ports LvdsFiltering Reference Voltage and Clocks Power DomainsDevelopment Tools Evaluation KIT Additional InformationPin Definitions-Clocks and Reset Signal Type Term DescriptionSclk Ratio RatioPin Definitions-External Port Bus Controls ACK T/ODSignal Type Pin Definitions-External Port ArbitrationPin Definitions-External Port DMA/Flyby DSP performs DMA transfers according to the DMASample the data instead of the TigerSHARC MakesPin Definitions-External Port Sdram Controller LdqmHdqm SDA10Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term DescriptionPin Definitions-Link Ports CONTROLIMP0CONTROLIMP1 DS1Pin Definitions-Power, Ground, and Reference Driver ModeDS2-0 Drive Output Pins Strength Impedance Impedance Control SelectionType at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Operating Conditions SclkvrefElectrical Characteristics Maximum Duty Cycle for Input Transient VoltageMaximum Duty VIN Max VIN Min Cycle2Package Information ESD SensitivityAbsolute Maximum Ratings Package Brand InformationTiming Specifications AC Asynchronous Signal SpecificationsGeneral AC Timing Reference Clocks-Core Clock Cclk Cycle TimeReference Clocks-System Clock Sclk Cycle Time Reference Clocks-JTAG Test Clock TCK Cycle TimeSclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Parameter Description Min Max UnitPower-Up Timing1 Power-Up Reset TimingNormal Reset Timing On-Chip Dram Refresh1AC Signal Specifications OutputDisable MaxDS2-0 Static Pins-Must Be Constant Strap PinsJtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 Strap SYS 9Link Port Lvds Transmit Electrical Characteristics Link Port Lvds Receive Electrical CharacteristicsParameter Description Test Conditions Min Max Unit VODLink Port-Data Out Timing Parameter Description Min Max UnitLink Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold FigureLink Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at StrengthOutput Disable Time Test ConditionsOutput Enable Time Capacitive LoadingTimes Andfall Rise Fall Time Thermal Characteristics Thermal Characteristics for 25 mm × 25 mm PackageEnvironmental Conditions Parameter Condition Typical UnitBall Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball AssignmentsSdcke SCLKRAT1 L0ACKOL0DATI1N L0DATI3NDS2 Enedreg TCK ID2 TDI TMR0EDS1 CONTROLIMP1 TDO FLAG3 L1CLKINNSurface Mount Design BGA Data for Use with Surface Mount DesignPackage Ball Attach Type Solder Mask Opening Ball Pad Size Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576Ordering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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