Analog Devices ADSP-TS201S Link Port-Data Out Timing, Parameter Description Min Max Unit

Page 31

ADSP-TS201S

Link Port—Data Out Timing

Table 32 with Figure 18, Figure 19, Figure 20, Figure 21,

Figure 22, and Figure 23 provide the data out timing for the

LVDS link ports.

Table 32. Link Port—Data Out Timing

Parameter

 

Description

Min

 

Max

Unit

Outputs

 

 

 

 

 

 

 

tREO

 

Rising Edge (Figure 19)

 

 

350

ps

tFEO

 

Falling Edge (Figure 19)

 

 

350

ps

tLCLKOP

 

LxCLKOUT Period (Figure 18)

Greater of 2.0 or

 

Smaller of 12.5 or

 

 

 

 

 

0.9 ⋅ LCR ⋅ tCCLK1, 2, 3

 

1.1 ⋅ LCR ⋅ tCCLK1, 2, 3

ns

tLCLKOH

 

LxCLKOUT High (Figure 18)

1

 

1

ns

 

0.4 ⋅ tLCLKOP

 

0.6 ⋅ tLCLKOP

tLCLKOL

 

LxCLKOUT Low (Figure 18)

1

 

1

ns

 

0.4 ⋅ tLCLKOP

 

0.6 ⋅ tLCLKOP

tCOJT

 

LxCLKOUT Jitter (Figure 18)

 

 

±1504, 5, 6

ps

 

 

 

 

 

 

±2507

ps

tLDOS

 

LxDATO Output Setup (Figure 20)

 

1, 4,

8

ns

 

0.25 ⋅ LCR ⋅ tCCLK – 0.10 ⋅ tCCLK

 

 

 

 

 

 

1, 5, 6, 8

ns

 

 

 

 

0.25 ⋅ LCR ⋅ tCCLK – 0.15 ⋅ tCCLK

 

 

 

 

 

0.25 ⋅ LCR ⋅ tCCLK – 0.30 ⋅

1,

7, 8

ns

 

 

 

 

tCCLK

 

tLDOH

 

LxDATO Output Hold (Figure 20)

 

1, 4, 8

ns

 

0.25 ⋅ LCR ⋅ tCCLK – 0.10 ⋅ tCCLK

 

 

 

 

 

 

1, 5, 6, 8

ns

 

 

 

 

0.25 ⋅ LCR ⋅ tCCLK – 0.15 ⋅ tCCLK

 

 

 

 

 

0.25 ⋅ LCR ⋅ tCCLK – 0.30 ⋅

1, 7, 8

ns

 

 

 

 

tCCLK

 

tLACKID

 

Delay from LxACKI rising edge to first transmission

 

 

1, 2

ns

 

 

 

16 ⋅ LCR ⋅ tCCLK

 

 

clock edge (Figure 21)

 

 

 

 

tBCMPOV

 

 

 

 

 

1, 2

 

 

LxBCMPO Valid (Figure 21)

 

 

ns

 

 

 

2 ⋅ LCR ⋅ tCCLK

tBCMPOH

 

 

Hold (Figure 22)

3 ⋅ TSW – 0.51, 9

 

 

ns

LxBCMPO

 

 

Inputs

 

 

 

 

 

 

 

tLACKIS

 

LxACKI low setup to guarantee that the transmitter

 

 

 

 

 

 

stops transmitting (Figure 22)

 

 

 

 

 

 

LxACKI high setup to guarantee that the transmitter

 

 

 

 

 

 

continues its transmission without any interruption

 

 

 

 

 

 

(Figure 23)

1, 2

 

 

ns

 

 

16 ⋅ LCR ⋅ tCCLK

 

 

tLACKIH

 

LxACKI High Hold Time (Figure 23)

0.51

 

 

ns

1Timing is relative to the 0 differential voltage (VOD = 0).

2LCR (link port clock ratio) = 1, 1.5, 2, or 4. tCCLK is the core period.

3For the cases of tLCLKOP = 2.0 ns and tLCLKOP = 12.5 ns, the effect of tCOJT specification on output period must be considered.

4 LCR= 1.

5 LCR= 1.5.

6 LCR= 2.

7 LCR= 4.

8The tLDOS and tLDOH values include LCLKOUT jitter.

9TSW is a short-word transmission period. For a 4-bit link, it is 2 ⋅ LCR ⋅ tCCLK. For a 1-bit link, it is 8 ⋅ LCR ⋅ tCCLK ns.

Rev. C Page 31 of 48 December 2006

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Contents ADSP-TS201S ADSP-TS201S FIR filter per real tap 83 ns General-Purpose Algorithm Benchmarks at 600 MHzClock Benchmark Speed CyclesData Alignment Buffer DAB Dual Compute BlocksDual Integer ALU Ialu Flexible Instruction Set Program SequencerDSP Memory Interrupt ControllerInternal Space External Port OFF-CHIP MEMORY/PERIPHERALS InterfaceSdram Controller DMA ControllerHost Interface Multiprocessor InterfaceDMA controller provides these additional features Link Ports Lvds Timer and GENERAL-PURPOSE I/OReset and Booting No Boot, Run from Memory AddressesFiltering Reference Voltage and Clocks Power DomainsDevelopment Tools Additional Information Evaluation KITRatio Pin Definitions-Clocks and ResetSignal Type Term Description Sclk RatioACK T/OD Pin Definitions-External Port Bus ControlsPin Definitions-External Port Arbitration Signal TypeMakes Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA Sample the data instead of the TigerSHARCSDA10 Pin Definitions-External Port Sdram ControllerLdqm HdqmPin Definitions-JTAG Port Signal Type Term Description Pin Definitions-Flags, Interrupts, and TimerDS1 Pin Definitions-Link PortsCONTROLIMP0 CONTROLIMP1Impedance Control Selection Pin Definitions-Power, Ground, and ReferenceDriver Mode DS2-0 Drive Output Pins Strength ImpedanceType at Signal Reset Pin Definitions-I/O Strap PinsPin Rstin = Sclkvref Operating ConditionsVIN Max VIN Min Cycle2 Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage Maximum DutyPackage Brand Information Package InformationESD Sensitivity Absolute Maximum RatingsReference Clocks-Core Clock Cclk Cycle Time Timing SpecificationsAC Asynchronous Signal Specifications General AC TimingParameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Sclkrat = 5⋅, 7⋅ Parameter Description Min Max UnitPower-Up Reset Timing Power-Up Timing1On-Chip Dram Refresh1 Normal Reset TimingOutputDisable Max AC Signal SpecificationsStrap SYS 9 DS2-0 Static Pins-Must Be ConstantStrap Pins Jtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0VOD Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit Link Port-Data Out TimingLink Ports-Output Clock Link Ports-Transmission End and Stops LxBCMPI Hold Figure Link Port-Data In TimingLink Ports-Data Input Setup and Hold1 Typical Drive Currents at Strength Output Drive CurrentsTest Conditions Output Disable TimeCapacitive Loading Output Enable TimeTimes Andfall Rise Fall Time Parameter Condition Typical Unit Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Environmental ConditionsBall Bgaed PIN Configurations Ball 25 mm × 25 mm Bgaed Ball Assignments Ball No Signal NameL0DATI3N Sdcke SCLKRAT1L0ACKO L0DATI1NL1CLKINN DS2 Enedreg TCKID2 TDI TMR0E DS1 CONTROLIMP1 TDO FLAG3Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Surface Mount DesignBGA Data for Use with Surface Mount Design Package Ball Attach Type Solder Mask Opening Ball Pad SizeOrdering Guide Temperature Instruction On-Chip Package Model Range1 Rate2Operating Voltage Option Description Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December
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